Impact of technology scaling on CMOS RF devices and circuits

In this paper, the RF/microwave performance of CMOS technology is examined as a function of the gate length. The following CMOS technologies are characterized and compared: 0.18 /spl mu/m, 0.25 /spl mu/m, 0.35 /spl mu/m, 0.5 /spl mu/m and 0.8 /spl mu/m. The unity current gain frequency scales as one over the effective gate length. The minimum noise figure is less than 1.5 dB at 2.0 GHz for gate lengths less than 0.5 /spl mu/m for both nMOS and pMOS transistors. The total device width required for conjugate noise matching is 400 /spl mu/m and 50 /spl mu/m for the 0.8 /spl mu/m and 0.18 /spl mu/m gate length, respectively. The current required for a 1.9 GHz cascode LNA is 15 mA and 2.7 mA for the 0.5 /spl mu/m and 0.18 /spl mu/m CMOS processes, respectively. This reduction in current is due to the fact that g/sub m//I/sub ds/ for a 0.18 /spl mu/m process is 25 V/sup -1/ whereas it is equal to 5 V/sup -1/ for a 0.5 /spl mu/m process. The advantage of using pMOS transistors is illustrated in a 1 volt RF front-end receiver.