Planar-Nothing On Insulator parasitic structure within a static induction transistor made by selective epitaxial growth

Power dissipation obstacle in electronic devices is strongly related to their internal breakdown mechanism. The Static Induction Transistor optimization imposes to reach p-gate regions as deep as vertical as possible. These objectives can be achieved using Selective Epitaxial Growth technology, so that the final structure between Gate and Drain becomes Silicon On Insulator. In addition the insulator is thin enough, it allows the vertical Gate–Drain breakdown, by a parasite planar variant of the Nothing On Insulator structure. Other papers have been presented Nothing On Insulator alternative structures alone for useful or non-parasitic applications. At this movement, the Nothing On Insulator structure has another role to play. It is the main parasitic device prevailing inside the Static Induction Transistor that must be avoided. The paper presents analytical models and simulation results for the potential distribution in a Gate–Drain cross-section. A breakdown regime is established for the Static Induction Transistor, with breakdown voltages between 313 V and 430 V, based on the planar-Nothing On Insulator theory.