利用移位寄存器准等效物的安全可测试扫描设计

Katsuya Fujiwara, H. Fujiwara, H. Tamamoto
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引用次数: 2

摘要

扫描设计使数字电路易于测试,然而,它也可以被利用来攻击芯片。我们已经报道了一种安全的、可测试的扫描设计方法,通过使用被称为“SR等效”的扩展移位寄存器,它在功能上等效,但在结构上不等同于移位寄存器(14)、(15)、(16)、(17)、(18)。在本文中,为了进一步扩展sr -等效电路的范畴,我们引入了一类更广泛的电路,称为“sr -准等效电路”,它仍然满足与sr -等效电路相似的可测试性和安全性。为了估计安全水平,我们澄清了几个线性结构电路的sr -准等价中每个等价类的基数,并给出了通过增强程序SREEP获得的sr -准等价的实际数量。
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Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents
Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by using extended shift registers called "SR- equivalents" that are functionally equivalent but not structurally equivalent to shift registers(14), (15), (16), (17), (18). In this paper, to further extend the class of SR-equivalents we introduce a wider class of circuits called "SR-quasi- equivalents" which still satisfy the testability and security similar to SR-equivalents. To estimate the security level, we clarify the cardinality of each equivalent class in SR-quasi-equivalents for several linear structural circuits, and also present the actual number of SR-quasi-equivalents obtained by the enhanced program SREEP.
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IPSJ Transactions on System LSI Design Methodology
IPSJ Transactions on System LSI Design Methodology Engineering-Electrical and Electronic Engineering
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