Modeling, characterization and design of monolithic inductors for silicon RFICs

The results of a comprehensive investigation into the characteristics and optimization of inductors fabricated in the top-level metal of a sub-micron silicon VLSI process are presented. A computer program which extracts a physically-based model of microstrip components which is suitable for circuit (SPICE) simulation has been used to evaluate variations in metallization, layout geometry and substrate parameters upon inductor performance. 3-D numerical simulations and experimental measurements of inductors were also used to benchmark the model accuracy. It is shown in this work that low inductor Q is primarily due to the restrictions imposed by the thin interconnect metallization available in most VLSI technologies, and that computer optimization of the inductor layout can be used to achieve a 50% improvement in component Q-factor over unoptimized designs.