{"title":"使用标准ASIC库元素、工具和设计方法设计高速串行端口","authors":"Paul Freud","doi":"10.1109/CICC.2000.852654","DOIUrl":null,"url":null,"abstract":"This paper describes a high-speed serial port design approach which uses standard ASIC libraries, tools and design methodologies. Leveraging existing backend ASIC tools and technology enabled us to place, route, and verify serial links running up to 622 Mb/s. Our approach has been implemented on multiple chips and validated with a detailed comparison of Spice to static timing analysis.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"34 1","pages":"227-230"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies\",\"authors\":\"Paul Freud\",\"doi\":\"10.1109/CICC.2000.852654\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a high-speed serial port design approach which uses standard ASIC libraries, tools and design methodologies. Leveraging existing backend ASIC tools and technology enabled us to place, route, and verify serial links running up to 622 Mb/s. Our approach has been implemented on multiple chips and validated with a detailed comparison of Spice to static timing analysis.\",\"PeriodicalId\":20702,\"journal\":{\"name\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"volume\":\"34 1\",\"pages\":\"227-230\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2000.852654\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852654","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Designing high-speed serial ports using standard ASIC library elements, tools and design methodologies
This paper describes a high-speed serial port design approach which uses standard ASIC libraries, tools and design methodologies. Leveraging existing backend ASIC tools and technology enabled us to place, route, and verify serial links running up to 622 Mb/s. Our approach has been implemented on multiple chips and validated with a detailed comparison of Spice to static timing analysis.
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