A robust digital delay line architecture in a 0.13 /spl mu/m CMOS technology node for reduced design and process sensitivities

The combination of high operating frequencies and low-power requirements for DSP cores targeted towards mobile applications makes clock synthesis and phase synchronization for these devices very challenging. These constraints make all-digital solutions (digital PLLs and DLLs) an attractive option (Dunning et al, 1995; Fried, 1996; Minami et al, 2000). This paper describes a digital delay-line architecture that can be used for these applications in a 0.11 /spl mu/m (silicon gate length) CMOS technology. Process variability and sensitivities increase at these geometries and it is difficult to meet target specifications across the entire spread of variations in process, voltages and temperatures (PVT corners). The design methodology presented in this paper minimizes these sensitivities.