利用CMOS器件噪声的65nm仲裁puf侧通道建模攻击

Jeroen Delvaux, I. Verbauwhede
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引用次数: 160

摘要

物理不可克隆函数(puf)正在作为硬件安全原语出现。对于所谓的强puf,在理想情况下,挑战响应对(CRPs)的数量随着所需的芯片面积呈指数增长。他们可以提供一种机制来验证芯片,这种芯片对于每个制造样品来说都是固有的独特的。然而,通过机器学习(ML)对CRP行为进行建模已被证明是一种威胁。在本文中,我们利用PUF响应的可重复性缺陷作为模型构建的侧通道。我们证明了65nm CMOS仲裁puf可以成功建模,而不使用任何ML算法。数据来源于真实世界的测量,而不是模拟。获得了超过97%的建模精度,这与之前发表的ML结果相当。所有强PUF设计都应考虑通过被利用侧通道的信息泄漏。联合攻击策略,即重复性测量促进ML,可能是有效的,并建议进一步研究。
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Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise
Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. For so-called strong PUFs, the number of challenge-response pairs (CRPs) increases exponentially with the required chip area in the ideal case. They can provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. Modeling of the CRP behavior through Machine Learning (ML) has shown to be a threat however. In this paper, we exploit repeatability imperfections of PUF responses as a side channel for model building. We demonstrate that 65nm CMOS arbiter PUFs can be modeled successfully, without utilizing any ML algorithm. Data originates from real-world measurements and hence not from simulations. Modeling accuracies exceeding 97% are obtained, which is comparable with previously published ML results. Information leakage through the exploited side channel should be considered for all strong PUF designs. Combined attack strategies, whereby repeatability measurements facilitate ML, might be effective and are recommended for further research.
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