Takahiro Yamamoto, Ittetsu Taniguchi, H. Tomiyama, S. Yamashita, Yuko Hara-Azumi
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A systematic methodology for design and analysis of approximate array multipliers
Approximate computing is considered as a promising approach to design of power-or area-efficient digital circuits. This paper proposes a systematic methodology for design and analysis of approximate array multipliers. Our methodology systematically designs a series of approximate array multipliers with different area, delay and accuracy characteristics so that an LSI designer can select the one which best fits to the requirements of her/his applications. Our experiments explore the trade-offs among area, delay and accuracy of the approximate multipliers.
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