一个有效的,宽范围的时间-数字转换器使用级联时间插值阶段电阻抗谱

Seongheon Shin, Soon-Jae Kweon, Jeong-Ho Park, Yong-Chang Choi, Hyung-Joun Yoo
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引用次数: 3

摘要

本文提出了一种用于电阻抗谱(EIS)系统极性解调的宽输入范围时间-数字转换器(TDC)的新结构。该系统结合了基于计数器的TDC和级联时间插值阶段,有效地量化了相位分量。从1 khz到2.048 mhz频率扫描范围的最大相位误差为0.52度,优于先前报道的。插值因子的可重构性和级联架构极大地提高了系统的硬件效率,平均功耗仅为1.93 mW,这对基于极性解调器的EIS系统的SoC实现具有一定的参考价值。
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An efficient, wide range time-to-digital converter using cascaded time-interpolation stages for electrical impedance spectroscopy
This paper proposes a novel architecture of time-to-digital converter (TDC) with wide input range in polar demodulators for electrical impedance spectroscopy (EIS) systems. The system combines a counter-based TDC with cascaded time interpolation stages and efficiently quantizes the phase component. The maximum phase error of 0.52 degrees from 1-kHz to 2.048-MHz frequency sweep range superior to previously reported ones. Reconfigurability of interpolation factor and cascaded architecture greatly enhances hardware efficiency of the system with average power consumption of 1.93 mW, which makes this work worth for system-on-chip (SoC) realization of EIS systems based on polar demodulators.
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