Jinuk Luke Shin, K. Tam, Dawei Huang, B. Petrick, H. Pham, C. Hwang, H. Li, Alan P. Smith, Timothy Johnson, F. Schumacher, D. Greenhill, A. Leon, Allan Strong
{"title":"40nm 16核128线程CMT SPARC SoC处理器","authors":"Jinuk Luke Shin, K. Tam, Dawei Huang, B. Petrick, H. Pham, C. Hwang, H. Li, Alan P. Smith, Timothy Johnson, F. Schumacher, D. Greenhill, A. Leon, Allan Strong","doi":"10.1109/ISSCC.2010.5434030","DOIUrl":null,"url":null,"abstract":"This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of cores, a larger L2 cache, and higher maximum I/O bandwidth, within the same power envelope. Sixteen 8-threaded enhanced SPARC cores (SPC) provide 128 threads in a single die, delivering the highest thread count for a general-purpose microprocessor. The new cache coherency further allows up to 4-way glueless systems with a total of 512 threads. Each core communicates with the unified 6MB L2 cache through a crossbar (CCX) delivering 461GB/s (Fig. 5.2.1). A gasket (CXG) is also introduced to manage the congestion and synchronization of the massive interconnect between the 16 cores and the crossbar. This facilitates a synchronized delay control between any core and any L2 bank for partial core product binning and testing.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"54 22","pages":"98-99"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"79","resultStr":"{\"title\":\"A 40nm 16-core 128-thread CMT SPARC SoC processor\",\"authors\":\"Jinuk Luke Shin, K. Tam, Dawei Huang, B. Petrick, H. Pham, C. Hwang, H. Li, Alan P. Smith, Timothy Johnson, F. Schumacher, D. Greenhill, A. Leon, Allan Strong\",\"doi\":\"10.1109/ISSCC.2010.5434030\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of cores, a larger L2 cache, and higher maximum I/O bandwidth, within the same power envelope. Sixteen 8-threaded enhanced SPARC cores (SPC) provide 128 threads in a single die, delivering the highest thread count for a general-purpose microprocessor. The new cache coherency further allows up to 4-way glueless systems with a total of 512 threads. Each core communicates with the unified 6MB L2 cache through a crossbar (CCX) delivering 461GB/s (Fig. 5.2.1). A gasket (CXG) is also introduced to manage the congestion and synchronization of the massive interconnect between the 16 cores and the crossbar. This facilitates a synchronized delay control between any core and any L2 bank for partial core product binning and testing.\",\"PeriodicalId\":6418,\"journal\":{\"name\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"volume\":\"54 22\",\"pages\":\"98-99\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"79\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2010.5434030\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5434030","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of cores, a larger L2 cache, and higher maximum I/O bandwidth, within the same power envelope. Sixteen 8-threaded enhanced SPARC cores (SPC) provide 128 threads in a single die, delivering the highest thread count for a general-purpose microprocessor. The new cache coherency further allows up to 4-way glueless systems with a total of 512 threads. Each core communicates with the unified 6MB L2 cache through a crossbar (CCX) delivering 461GB/s (Fig. 5.2.1). A gasket (CXG) is also introduced to manage the congestion and synchronization of the massive interconnect between the 16 cores and the crossbar. This facilitates a synchronized delay control between any core and any L2 bank for partial core product binning and testing.