40nm 16核128线程CMT SPARC SoC处理器

Jinuk Luke Shin, K. Tam, Dawei Huang, B. Petrick, H. Pham, C. Hwang, H. Li, Alan P. Smith, Timothy Johnson, F. Schumacher, D. Greenhill, A. Leon, Allan Strong
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引用次数: 79

摘要

下一代芯片多线程(CMT) SPARC SoC处理器,代号为Rainbow Falls,片上线程数比其前身UltraSparc T2+增加了一倍。在相同的功率范围内,该芯片提供了高水平的集成和可扩展性,具有两倍的内核数量,更大的L2缓存和更高的最大I/O带宽。16个8线程增强型SPARC内核(SPC)在单个模具中提供128个线程,为通用微处理器提供最高的线程数。新的缓存一致性进一步允许总共512个线程的4路无胶合系统。每个核心通过传输461GB/s的交叉排(CCX)与统一的6MB L2缓存通信(图5.2.1)。此外,还引入了一个衬垫(CXG)来管理16芯与横杆之间大量互连的拥塞和同步。这有助于在任何核心和任何L2组之间进行同步延迟控制,用于部分核心产品的分组和测试。
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A 40nm 16-core 128-thread CMT SPARC SoC processor
This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of cores, a larger L2 cache, and higher maximum I/O bandwidth, within the same power envelope. Sixteen 8-threaded enhanced SPARC cores (SPC) provide 128 threads in a single die, delivering the highest thread count for a general-purpose microprocessor. The new cache coherency further allows up to 4-way glueless systems with a total of 512 threads. Each core communicates with the unified 6MB L2 cache through a crossbar (CCX) delivering 461GB/s (Fig. 5.2.1). A gasket (CXG) is also introduced to manage the congestion and synchronization of the massive interconnect between the 16 cores and the crossbar. This facilitates a synchronized delay control between any core and any L2 bank for partial core product binning and testing.
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