Empirical Study of the Cut-Off Frequency of Multi-Finger Nanometer MOS Transistor

Multi-finger gate structure has been extensively applied to layout MOS transistors in RF analog circuits. The main advantage of this method is that a large drain current can be obtained with a compact silicon area. Furthermore, because of the reduced gate resistance, the cut-off frequency obtained from the multi-finger layout MOS transistor is higher than that of a single-finger transistor. This work will provide an empirical study on the impact of multi-finger layout on cut-off frequency for nanometer MOS transistors. It is shown that increasing the number of fingers in multi-finger layout has diminishing returns, and there exists an optimal number of fingers to achieve the highest cut-off frequency, and hence the RF performance of the transistor.