使用14个cnfet的快速节能全加法器电路

Jitendra Kumar Saini , Avireni Srinivasulu , Renu Kumawat
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引用次数: 2

摘要

随着对更快,高效和强大的计算设备的需求不断增加,电路设计的工业研究面临着尺寸,功率,效率和可扩展性等挑战。设计师有一系列的选择,利用不同的设计方法,材料或技术来满足这些需求。近年来,碳纳米管场效应晶体管(CNFET)已成为设计高速、低功耗和低成本电路的一种临时替代方案。本文提出了一种使用14个cnfet的1位全加法器电路(1b-FA),以改进上述特性。采用32 nm CNFET技术,在电源电压(VDD)为+0.9V的条件下,利用Cadence Virtuoso CAD工具对该设计进行了仿真。从功率、延迟和功率延迟积(PDP)的角度对各种现有全加法器设计进行了性能分析。通过对CNFET直径(DCNT)和阈值电压(Vth)的参数变化来分析输出稳定性。此外,采用1b-FA实现了(n = 4,8,16,32)的n位纹波进位加法器(nb-RCA),并与现有的nb-RCA进行了比较,分析了性能和效率。后来加入了1b-FA输出自动纠错等功能。
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Fast and energy efficient full adder circuit using 14 CNFETs

With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (VDD) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (DCNT) and threshold voltage (Vth) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.

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