1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique

Pub Date : 1999-10-27 DOI: 10.1109/SOI.1999.819860 S. Liu, J. Kuo

An SOI nano flash memory device

Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819872 Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge

Defect analysis of patterned SOI material

Pub Date : 1999-10-04 DOI: 10.1109/SOI.1999.819882 S. Bagchi, Y. Yu, M. Mendicino, J. Conner, A. Anderson, L. Prabhu, M. Tiner, M. Alles