Summary form only given. This paper reports a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using a partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM, as verified by MEDICI results.
{"title":"A novel 0.7 V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique","authors":"S. Liu, J. Kuo","doi":"10.1109/SOI.1999.819860","DOIUrl":"https://doi.org/10.1109/SOI.1999.819860","url":null,"abstract":"Summary form only given. This paper reports a novel low-voltage two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access capability using a partially-depleted SOI CMOS dynamic-threshold technique. With an innovative approach connecting the body terminal of an NMOS device in the latch and the write access pass transistor to the write word line, this 6T memory cell can be used to provide SBLSRWA capability for 0.7 V two-port SOI CMOS VLSI SRAM, as verified by MEDICI results.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge
Several nano flash memory devices have been reported in the literature (Nakajima et al. 1996; Guo et al. 1996; Welser et al. 1997). These devices are basically miniature EEPROM cells in which electrons are injected in a floating storage node by tunnel effect through an oxide layer. The variation of the potential of the floating node due to electron injection modifies the threshold voltage of a thin and narrow SOI MOSFET, which makes it possible to store information in the device. This paper describes the fabrication of an SOI nano flash memory device using Unibond/sup (R)/ wafers and e-beam lithography. The device can be programmed and erased using 5 V gate voltage pulses. The area of the active storage region is 150 nm/spl times/150 nm.
文献中已经报道了几种纳米闪存器件(Nakajima et al. 1996;Guo et al. 1996;Welser et al. 1997)。这些设备基本上是微型EEPROM电池，其中电子通过氧化层的隧道效应注入到浮动存储节点中。由于电子注入引起的浮节点电位的变化改变了薄而窄的SOI MOSFET的阈值电压，这使得在器件中存储信息成为可能。本文介绍了利用Unibond/sup (R)/晶圆和电子束光刻技术制备SOI纳米闪存器件。该器件可以使用5v栅极电压脉冲进行编程和擦除。活性存储区面积为150nm /spl倍/ 150nm。
{"title":"An SOI nano flash memory device","authors":"Xiaohui Tang, X. Baie, V. Bayot, F. van de Wiele, J. Colinge","doi":"10.1109/SOI.1999.819872","DOIUrl":"https://doi.org/10.1109/SOI.1999.819872","url":null,"abstract":"Several nano flash memory devices have been reported in the literature (Nakajima et al. 1996; Guo et al. 1996; Welser et al. 1997). These devices are basically miniature EEPROM cells in which electrons are injected in a floating storage node by tunnel effect through an oxide layer. The variation of the potential of the floating node due to electron injection modifies the threshold voltage of a thin and narrow SOI MOSFET, which makes it possible to store information in the device. This paper describes the fabrication of an SOI nano flash memory device using Unibond/sup (R)/ wafers and e-beam lithography. The device can be programmed and erased using 5 V gate voltage pulses. The area of the active storage region is 150 nm/spl times/150 nm.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115499180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Bagchi, Y. Yu, M. Mendicino, J. Conner, A. Anderson, L. Prabhu, M. Tiner, M. Alles
SOI technology has several advantages over bulk Si, including potentially lower leakage, higher speed, freedom from latch-up, and lowered parasitic capacitance. However, issues such as floating body effects, poorer thermal conductivity, lack of device libraries, etc., can complicate operation, processing, and design of certain devices fabricated on SOI wafers. In such a situation, it may be desirable to have those parts of the circuits that can take advantage of SOI fabricated separately from the other circuits on bulk Si. The traditional approach is a multichip module (MCM), with sub-units fabricated on the appropriate substrate. This can add considerably to the cost and complexity of the final product. An elegant alternative approach is a patterned SOI wafer. Such a wafer has bulk Si areas interspersed with SOI areas, or "pads", of desired dimensions. Several technologies have been proposed for fabrication of such wafers (Van Bentum and Vogt, 1998). Perhaps the most promising of them is patterned SIMOX. SIMOX has emerged as a mature processing technology for the production of SOI wafers. Prior to design of device layouts, it is important to take into consideration the type, density, and location of crystalline defects which might be present in the region of transition from bulk Si to the SOI pads. In this paper, we report the results of our investigation of crystalline defects in patterned SIMOX wafers.
{"title":"Defect analysis of patterned SOI material","authors":"S. Bagchi, Y. Yu, M. Mendicino, J. Conner, A. Anderson, L. Prabhu, M. Tiner, M. Alles","doi":"10.1109/SOI.1999.819882","DOIUrl":"https://doi.org/10.1109/SOI.1999.819882","url":null,"abstract":"SOI technology has several advantages over bulk Si, including potentially lower leakage, higher speed, freedom from latch-up, and lowered parasitic capacitance. However, issues such as floating body effects, poorer thermal conductivity, lack of device libraries, etc., can complicate operation, processing, and design of certain devices fabricated on SOI wafers. In such a situation, it may be desirable to have those parts of the circuits that can take advantage of SOI fabricated separately from the other circuits on bulk Si. The traditional approach is a multichip module (MCM), with sub-units fabricated on the appropriate substrate. This can add considerably to the cost and complexity of the final product. An elegant alternative approach is a patterned SOI wafer. Such a wafer has bulk Si areas interspersed with SOI areas, or \"pads\", of desired dimensions. Several technologies have been proposed for fabrication of such wafers (Van Bentum and Vogt, 1998). Perhaps the most promising of them is patterned SIMOX. SIMOX has emerged as a mature processing technology for the production of SOI wafers. Prior to design of device layouts, it is important to take into consideration the type, density, and location of crystalline defects which might be present in the region of transition from bulk Si to the SOI pads. In this paper, we report the results of our investigation of crystalline defects in patterned SIMOX wafers.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123116343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ushiki, K. Kotani, T. Funaki, K. Kawai, T. Ohmi
As the trend in SOI technology continues to be towards thin-film devices, it is important to take a closer look at the electrically active defects at SOI-BOX interface, which could strongly affect the performance and reliability of SOI devices (Cristoloveanu, 1995). Although several studies on the interface trap densities at the SOI-BOX interface of SIMOX wafers have been reported (Nakashima et al, 1998; Yang et al., 1992), comprehensive analysis of these electrically active defects has not yet been fully studied, despite its scientific interest and technological importance. The purpose of this paper is to show for the first time that extraordinary kink effects have been experimentally observed in back-gate transconductance (g/sub m2/) characteristics of fully-depleted (FD) SOI MOS transistors on high-dose SIMOX wafers, and a physical explanation has been found.
随着SOI技术继续向薄膜器件发展，仔细研究SOI- box接口上的电活性缺陷非常重要，这些缺陷可能会严重影响SOI器件的性能和可靠性(Cristoloveanu, 1995)。虽然已经报道了一些关于SIMOX晶圆SOI-BOX界面陷阱密度的研究(Nakashima et al .， 1998;Yang et al.， 1992)，对这些电活性缺陷的全面分析尚未得到充分研究，尽管它具有科学意义和技术重要性。本文的目的是首次在实验中观察到高剂量SIMOX晶圆上全耗尽(FD) SOI MOS晶体管的反向跨导(g/sub m2/)特性中的异常扭结效应，并找到了物理解释。
{"title":"Evidence of energetically-localized trap-states at SOI-BOX interface in high-dose SIMOX wafers","authors":"T. Ushiki, K. Kotani, T. Funaki, K. Kawai, T. Ohmi","doi":"10.1109/SOI.1999.819852","DOIUrl":"https://doi.org/10.1109/SOI.1999.819852","url":null,"abstract":"As the trend in SOI technology continues to be towards thin-film devices, it is important to take a closer look at the electrically active defects at SOI-BOX interface, which could strongly affect the performance and reliability of SOI devices (Cristoloveanu, 1995). Although several studies on the interface trap densities at the SOI-BOX interface of SIMOX wafers have been reported (Nakashima et al, 1998; Yang et al., 1992), comprehensive analysis of these electrically active defects has not yet been fully studied, despite its scientific interest and technological importance. The purpose of this paper is to show for the first time that extraordinary kink effects have been experimentally observed in back-gate transconductance (g/sub m2/) characteristics of fully-depleted (FD) SOI MOS transistors on high-dose SIMOX wafers, and a physical explanation has been found.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117170119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. Predictions and analysis of the temperature field in a SOI device can be performed at several levels of complexity. Numerical simulations (e.g. Berger and Chai, 1991) and analytical methods (e.g. Goodson and Flik, 1992) have been used extensively to estimate the temperature field in a SOI device with different levels of accuracy. Numerical simulations of the temperature field in a SOI device can precisely determine the hot spots in a transistor, if proper thermal properties and accurate modeling of the heat generation in the device are considered. The analytical methods can provide physical insights into the effect of SOI device dimensions and thermal properties on the device temperature rise. This work aims to demonstrate the impact of the size effect on the thermal conductivity of thin silicon layers and subsequently on the SOI device thermal resistance.
{"title":"Thermal modeling of thin-film SOI transistors","authors":"M. Asheghi, P. Sverdrup, K. Goodson","doi":"10.1109/SOI.1999.819842","DOIUrl":"https://doi.org/10.1109/SOI.1999.819842","url":null,"abstract":"Summary form only given. Predictions and analysis of the temperature field in a SOI device can be performed at several levels of complexity. Numerical simulations (e.g. Berger and Chai, 1991) and analytical methods (e.g. Goodson and Flik, 1992) have been used extensively to estimate the temperature field in a SOI device with different levels of accuracy. Numerical simulations of the temperature field in a SOI device can precisely determine the hot spots in a transistor, if proper thermal properties and accurate modeling of the heat generation in the device are considered. The analytical methods can provide physical insights into the effect of SOI device dimensions and thermal properties on the device temperature rise. This work aims to demonstrate the impact of the size effect on the thermal conductivity of thin silicon layers and subsequently on the SOI device thermal resistance.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130579878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X.-L. Xu, R. Widenhofer, Y. Yu, O. Zia, S. Pozder, D. Hall, M. Rashed, D. Chang, S. Jallepalli, D. Connelly, T. Van Gompel, M. Olivares, M. Mendicino, J. Candelaria, S. Veeraraghavan, D. Dow
We report high performance device characteristics of 0.18 /spl mu/m SOI CMOS technology with indium (In) and antimony (Sb) retrograde channel doping and argon (Ar) implant. Experimental results demonstrate significant suppression of floating body (FB) effects, reduced off-state current, improved I/sub on/-I/sub off/ characteristics, and reduced drain induced barrier lowering (DIBL) values for the Ar implanted SOI devices. At the same time, the presence of Ar leads to increased subthreshold swing (SS), degraded GIDL characteristics, and increased electrical gate oxide thickness. Experimental results also show that the Ar implant for suppression of FB effects in PD SOI NMOS devices is less significant as the device gate channel length reduces to 0.15 /spl mu/m and below.
本文报道了采用铟(In)和锑(Sb)逆行通道掺杂和氩(Ar)植入的0.18 /spl mu/m SOI CMOS技术的高性能器件特性。实验结果表明，Ar植入的SOI器件明显抑制了浮体(FB)效应，降低了关断电流，改善了I/sub on/ I/sub off/特性，降低了漏极诱导势垒降低(DIBL)值。同时，Ar的存在导致亚阈值摆动(SS)增加，GIDL特性降低，电栅氧化层厚度增加。实验结果还表明，当器件栅极通道长度减小到0.15 /spl mu/m及以下时，Ar植入对PD SOI NMOS器件中FB效应的抑制作用较弱。
{"title":"Performance trade-offs of argon implanted SOI MOSFETs with In and Sb retrograde channel doping","authors":"X.-L. Xu, R. Widenhofer, Y. Yu, O. Zia, S. Pozder, D. Hall, M. Rashed, D. Chang, S. Jallepalli, D. Connelly, T. Van Gompel, M. Olivares, M. Mendicino, J. Candelaria, S. Veeraraghavan, D. Dow","doi":"10.1109/SOI.1999.819867","DOIUrl":"https://doi.org/10.1109/SOI.1999.819867","url":null,"abstract":"We report high performance device characteristics of 0.18 /spl mu/m SOI CMOS technology with indium (In) and antimony (Sb) retrograde channel doping and argon (Ar) implant. Experimental results demonstrate significant suppression of floating body (FB) effects, reduced off-state current, improved I/sub on/-I/sub off/ characteristics, and reduced drain induced barrier lowering (DIBL) values for the Ar implanted SOI devices. At the same time, the presence of Ar leads to increased subthreshold swing (SS), degraded GIDL characteristics, and increased electrical gate oxide thickness. Experimental results also show that the Ar implant for suppression of FB effects in PD SOI NMOS devices is less significant as the device gate channel length reduces to 0.15 /spl mu/m and below.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123706817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Yoshimura, K. Ueda, T. Nakura, K. Kubo, K. Mashiko, S. Maeda, S. Maegawa, Y. Yamaguchi, Y. Matsuda
Summary form only given. This paper shows a 2.5 GHz PLL circuit for high-speed communication devices using a 0.18 /spl mu/m SOI/CMOS technology. The technology uses a shallow trench structure to effectively isolate active devices on a thin film SOI substrate. We employed floating-body SOI/CMOS in this chip. We applied a ring oscillator for the voltage controlled-oscillator (VCO). The well-known issues of SOI do not affect the circuit stability and noise performance of our PLL circuit for several reasons. Firstly, as the frequency range required for the VCO is comparatively narrow, the floating-body configuration would have little effect on circuit operation (Ueda et al., 1996). Secondly, thermal equilibrium on the ring oscillator can be achieved within a few microseconds (Tenbroek et al., 1998). Then the self-heating issue would be insignificant for the lock-in process of the PLL. Besides this, the buried oxide of SOI and shallow trench isolation reduces the crosstalk noise from the large digital logic block which is the most potentially serious problem for system-level integration of sensitive circuits and large logic blocks.
只提供摘要形式。本文介绍了一种采用0.18 /spl mu/m SOI/CMOS技术的高速通信器件的2.5 GHz锁相环电路。该技术使用浅沟槽结构有效地隔离薄膜SOI衬底上的有源器件。我们在芯片中采用了浮体SOI/CMOS。我们采用环形振荡器作为压控振荡器(VCO)。众所周知的SOI问题不会影响我们的锁相环电路的稳定性和噪声性能，原因有几个。首先，由于VCO所需的频率范围比较窄，因此浮体结构对电路运行的影响不大(Ueda et al.， 1996)。其次，环形振荡器上的热平衡可以在几微秒内实现(Tenbroek et al.， 1998)。那么自热问题对于锁相环的锁相过程将是微不足道的。此外，SOI的埋藏氧化物和浅沟槽隔离降低了大型数字逻辑块的串扰噪声，这是敏感电路和大型逻辑块的系统级集成中最潜在的严重问题。
{"title":"A 1.8 V 2.5 GHz PLL using 0.18 /spl mu/m SOI/CMOS technology","authors":"K. Yoshimura, K. Ueda, T. Nakura, K. Kubo, K. Mashiko, S. Maeda, S. Maegawa, Y. Yamaguchi, Y. Matsuda","doi":"10.1109/SOI.1999.819834","DOIUrl":"https://doi.org/10.1109/SOI.1999.819834","url":null,"abstract":"Summary form only given. This paper shows a 2.5 GHz PLL circuit for high-speed communication devices using a 0.18 /spl mu/m SOI/CMOS technology. The technology uses a shallow trench structure to effectively isolate active devices on a thin film SOI substrate. We employed floating-body SOI/CMOS in this chip. We applied a ring oscillator for the voltage controlled-oscillator (VCO). The well-known issues of SOI do not affect the circuit stability and noise performance of our PLL circuit for several reasons. Firstly, as the frequency range required for the VCO is comparatively narrow, the floating-body configuration would have little effect on circuit operation (Ueda et al., 1996). Secondly, thermal equilibrium on the ring oscillator can be achieved within a few microseconds (Tenbroek et al., 1998). Then the self-heating issue would be insignificant for the lock-in process of the PLL. Besides this, the buried oxide of SOI and shallow trench isolation reduces the crosstalk noise from the large digital logic block which is the most potentially serious problem for system-level integration of sensitive circuits and large logic blocks.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128666192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
By masking the gate dielectric area of MOS devices during hydrogen implantation, patterned ion-cut can transfer processed IC device layers to other substrates (Lee et al. 1996; Roberds et al. 1998; Yun et al. 1998). Previous results showed that a 16 /spl mu/m/spl times/16 /spl mu/m nonimplanted region can be cleaved with a 4 /spl mu/m implanted area surrounding it. However, surface morphology of the cleaved Si(100) samples was rough, with a total thickness variation (TTV) of /spl sim/0.4 /spl mu/m for a 1.3 /spl mu/m-thick silicon layer transfer. In order to improve the roughness, we have investigated the fractional implantation area (FIA) effects on the transferred layer surface morphology.
通过在氢注入过程中掩盖MOS器件的栅极介电面积，图案离子切割可以将加工过的IC器件层转移到其他衬底上(Lee et al. 1996;roberts et al. 1998;Yun et al. 1998)。先前的研究结果表明，在16 /spl mu/m/spl倍/16 /spl mu/m的非植入区周围可切割出4 /spl mu/m的植入区。然而，切割后的Si(100)样品表面形貌粗糙，总厚度变化(TTV)为/spl sim/0.4 /spl mu/m，厚度为1.3 /spl mu/m。为了提高表面粗糙度，研究了分数注入面积(FIA)对转移层表面形貌的影响。
{"title":"Fractional implantation area effects on patterned ion-cut silicon layer transfer","authors":"C. Yun, N. Cheung","doi":"10.1109/SOI.1999.819886","DOIUrl":"https://doi.org/10.1109/SOI.1999.819886","url":null,"abstract":"By masking the gate dielectric area of MOS devices during hydrogen implantation, patterned ion-cut can transfer processed IC device layers to other substrates (Lee et al. 1996; Roberds et al. 1998; Yun et al. 1998). Previous results showed that a 16 /spl mu/m/spl times/16 /spl mu/m nonimplanted region can be cleaved with a 4 /spl mu/m implanted area surrounding it. However, surface morphology of the cleaved Si(100) samples was rough, with a total thickness variation (TTV) of /spl sim/0.4 /spl mu/m for a 1.3 /spl mu/m-thick silicon layer transfer. In order to improve the roughness, we have investigated the fractional implantation area (FIA) effects on the transferred layer surface morphology.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132414544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Making contact to the body of a partially depleted (PD) SOI transistor offers another degree of design freedom. For example, DTMOS (Assaderaghi et al., 1994) has demonstrated that the body-contact can be used to enhance the power/delay performance. It has also been shown that the body-contact plays an important role in eliminating the floating-body instability (Chuang, 1998) for sensitive circuits. A complete SPICE model that explicitly addresses the nonidealities of the body-contact is surely needed for SOI circuit design. Here, we present a compact body-contact SOI MOSFET model that has been implemented in BSIMPD2.0 for circuit simulation.
与部分耗尽(PD) SOI晶体管的本体接触提供了另一种程度的设计自由度。例如，DTMOS (Assaderaghi et al.， 1994)已经证明，身体接触可以用来提高功率/延迟性能。研究还表明，对于敏感电路，身体接触在消除浮体不稳定性方面起着重要作用(Chuang, 1998)。SOI电路设计肯定需要一个完整的SPICE模型来明确地解决身体接触的非理想性。在这里，我们提出了一个紧凑的体接触SOI MOSFET模型，该模型已在BSIMPD2.0中实现，用于电路仿真。
{"title":"A body-contact SOI MOSFET model for circuit simulation","authors":"P. Su, S. Fung, F. Assaderaghi, C. Hu","doi":"10.1109/SOI.1999.819853","DOIUrl":"https://doi.org/10.1109/SOI.1999.819853","url":null,"abstract":"Making contact to the body of a partially depleted (PD) SOI transistor offers another degree of design freedom. For example, DTMOS (Assaderaghi et al., 1994) has demonstrated that the body-contact can be used to enhance the power/delay performance. It has also been shown that the body-contact plays an important role in eliminating the floating-body instability (Chuang, 1998) for sensitive circuits. A complete SPICE model that explicitly addresses the nonidealities of the body-contact is surely needed for SOI circuit design. Here, we present a compact body-contact SOI MOSFET model that has been implemented in BSIMPD2.0 for circuit simulation.","PeriodicalId":117832,"journal":{"name":"1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1999-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Chang, Byonug Min, S. Veeraraghavan, M. Mendicino, T. Cooper, S. Egley, K. Cox
The CMOS gate delay on SOI depends on the switching history of floating-body transistors, which introduces uncertainty in predicting the performance of SOI-based circuits (Suh and Fossum, 1994; Shahidi et al., 1999). The main cause of the hysteretic delay is due to the transient variation of the body voltage during switching and the corresponding threshold voltage change. Since the capacitance coupling and generation/recombination currents determining the transient body-voltage are strong functions of temperature, the gate delay is also expected to show a significant temperature dependence. In the measurement of a 610-stage floating-body SOI CMOS open-ended inverter chain, we have observed that the hysteretic gate delay variation is worse at higher temperature for devices which showed pulse compression at room temperature. In this work, we have performed simulations to predict fast/slow gate delays for different SOI device structures versus temperature, and compared these results to measurements, thus illustrating the importance of accounting for temperature in history effects.
SOI上的CMOS栅极延迟取决于浮体晶体管的开关历史，这在预测基于SOI的电路的性能时引入了不确定性(Suh和Fossum, 1994;Shahidi et al.， 1999)。产生滞后延迟的主要原因是开关过程中体电压的瞬态变化和相应的阈值电压的变化。由于电容耦合和产生/复合电流决定瞬态体电压是温度的强函数，因此门延迟也预计会显示出显著的温度依赖性。在对610级浮体SOI CMOS开放式逆变器链的测量中，我们观察到在室温下表现出脉冲压缩的器件在更高温度下的滞回门延迟变化更差。在这项工作中，我们进行了模拟，以预测不同SOI器件结构对温度的快/慢栅极延迟，并将这些结果与测量结果进行了比较，从而说明了在历史效应中考虑温度的重要性。
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