Defect analysis of patterned SOI material

Abstract

SOI technology has several advantages over bulk Si, including potentially lower leakage, higher speed, freedom from latch-up, and lowered parasitic capacitance. However, issues such as floating body effects, poorer thermal conductivity, lack of device libraries, etc., can complicate operation, processing, and design of certain devices fabricated on SOI wafers. In such a situation, it may be desirable to have those parts of the circuits that can take advantage of SOI fabricated separately from the other circuits on bulk Si. The traditional approach is a multichip module (MCM), with sub-units fabricated on the appropriate substrate. This can add considerably to the cost and complexity of the final product. An elegant alternative approach is a patterned SOI wafer. Such a wafer has bulk Si areas interspersed with SOI areas, or "pads", of desired dimensions. Several technologies have been proposed for fabrication of such wafers (Van Bentum and Vogt, 1998). Perhaps the most promising of them is patterned SIMOX. SIMOX has emerged as a mature processing technology for the production of SOI wafers. Prior to design of device layouts, it is important to take into consideration the type, density, and location of crystalline defects which might be present in the region of transition from bulk Si to the SOI pads. In this paper, we report the results of our investigation of crystalline defects in patterned SIMOX wafers.