2010 IEEE International Integrated Reliability Workshop Final Report

Characterization of anomalous erase effects in 48 nm TANOS memory cells

Pub Date : 2010-10-01 DOI: 10.1109/IIRW.2010.5706494 Douglas A. Loehr, R. Hoffmann, A. Naumann, J. Paul, K. Seidel, M. Czernohorsky, V. Beyer

Recovery of negative and positive bias temperature stress in pMOSFETs

Pub Date : 2010-10-01 DOI: 10.1109/IIRW.2010.5706473 P. Hehenberger, H. Reisinger, T. Grasser

Impact of the storage layer charging on Random Telegraph Noise behavior of sub-50nm charge-trap-based TANOS and floating-gate memory cells

Pub Date : 2010-10-01 DOI: 10.1109/IIRW.2010.5706496 K. Seidel, R. Hoffmann, A. Naumann, J. Paul, D. Lohr, M. Czernohorsky, V. Beyer