Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706494
Douglas A. Loehr, R. Hoffmann, A. Naumann, J. Paul, K. Seidel, M. Czernohorsky, V. Beyer
On TANOS (Tantalum Alumina Nitride Oxide Silicon) charge trap cells an anomalous effect is observed during cell erase operation. Different TANOS cell architectures are investigated including an encapsulation liner of different thickness. Especially on cells fabricated without such a liner an unintended programming is observed and characterized in detail. A new characterization method is proposed to analyze this anomalous erase effect observed as an “erase hump” in transient erase characteristics. This effect is studied and discussed in correlation with liner thickness and cell retention behavior supported by electrical field simulations for cell erase conditions.
{"title":"Characterization of anomalous erase effects in 48 nm TANOS memory cells","authors":"Douglas A. Loehr, R. Hoffmann, A. Naumann, J. Paul, K. Seidel, M. Czernohorsky, V. Beyer","doi":"10.1109/IIRW.2010.5706494","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706494","url":null,"abstract":"On TANOS (Tantalum Alumina Nitride Oxide Silicon) charge trap cells an anomalous effect is observed during cell erase operation. Different TANOS cell architectures are investigated including an encapsulation liner of different thickness. Especially on cells fabricated without such a liner an unintended programming is observed and characterized in detail. A new characterization method is proposed to analyze this anomalous erase effect observed as an “erase hump” in transient erase characteristics. This effect is studied and discussed in correlation with liner thickness and cell retention behavior supported by electrical field simulations for cell erase conditions.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130076824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706473
P. Hehenberger, H. Reisinger, T. Grasser
Based on the asymmetric recovery behavior observed following negative and positive bias temperature stress in pMOSFETs, various stress tests with different stress times, oxide electric fields, and oxide thicknesses were performed. In contrast to NBTI, where the relaxation of the threshold voltage often follows a logarithmic behavior, PBTI stress reveals no logarithmic recovery. Notable relaxation after PBTI stress instead appears to happen later but faster. This asymmetry is more pronounced at harsher stress conditions, e.g. increasing stress time and oxide electric field. This can be explained by the different relative measurement windows for NBTI and PBTI, which depend on the stress time and the oxide electric field. A closer analysis of the recovery yields the spectra of capture and emission time constants of the underlying defects. We analyze the dependence of these spectra on the stress time and the oxide electric field, where the emission times of the defects are shifted towards smaller times for higher oxide electric field.
{"title":"Recovery of negative and positive bias temperature stress in pMOSFETs","authors":"P. Hehenberger, H. Reisinger, T. Grasser","doi":"10.1109/IIRW.2010.5706473","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706473","url":null,"abstract":"Based on the asymmetric recovery behavior observed following negative and positive bias temperature stress in pMOSFETs, various stress tests with different stress times, oxide electric fields, and oxide thicknesses were performed. In contrast to NBTI, where the relaxation of the threshold voltage often follows a logarithmic behavior, PBTI stress reveals no logarithmic recovery. Notable relaxation after PBTI stress instead appears to happen later but faster. This asymmetry is more pronounced at harsher stress conditions, e.g. increasing stress time and oxide electric field. This can be explained by the different relative measurement windows for NBTI and PBTI, which depend on the stress time and the oxide electric field. A closer analysis of the recovery yields the spectra of capture and emission time constants of the underlying defects. We analyze the dependence of these spectra on the stress time and the oxide electric field, where the emission times of the defects are shifted towards smaller times for higher oxide electric field.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132741462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706496
K. Seidel, R. Hoffmann, A. Naumann, J. Paul, D. Lohr, M. Czernohorsky, V. Beyer
Random Telegraph Noise (RTN) characterization was performed on charge-trap-based TANOS memory cells. The analysis results of cycle stress dependence and cell size scaling are discussed based on single cell measurements. Comparing charge-trap and floating-gate memory technologies different behavior for RTN was obtained. On charge-trap cells a threshold voltage dependence and superimposed noise was observed and is discussed based on measurement results and different cell architectures.
{"title":"Impact of the storage layer charging on Random Telegraph Noise behavior of sub-50nm charge-trap-based TANOS and floating-gate memory cells","authors":"K. Seidel, R. Hoffmann, A. Naumann, J. Paul, D. Lohr, M. Czernohorsky, V. Beyer","doi":"10.1109/IIRW.2010.5706496","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706496","url":null,"abstract":"Random Telegraph Noise (RTN) characterization was performed on charge-trap-based TANOS memory cells. The analysis results of cycle stress dependence and cell size scaling are discussed based on single cell measurements. Comparing charge-trap and floating-gate memory technologies different behavior for RTN was obtained. On charge-trap cells a threshold voltage dependence and superimposed noise was observed and is discussed based on measurement results and different cell architectures.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128894144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706511
Xiaochen Zhang, S. Yue, Liang Wang, Jiancheng Li
In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted. Results indicate that the reverse-biased drain region is sensitive to SEU, as well as the gate region. The largest amount of charge collection in device and the lowest LET threshold of SEU in SRAM both occur when the ion strikes at the drain/body junction area and passes through the centre part of the reverse junction.
{"title":"3D simulation of charge collection and SEU of 0.13µm partially depleted SOI SRAM","authors":"Xiaochen Zhang, S. Yue, Liang Wang, Jiancheng Li","doi":"10.1109/IIRW.2010.5706511","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706511","url":null,"abstract":"In this paper, the charge collection and parasitic bipolar effect of SOI NMOS devices in case of different ion strike locations have been analyzed through 3D simulation. The simulation results show that the strike at drain region can cause charge collection comparable with the collection induced by strike at the gate region above body. Single event upset (SEU) simulations of SRAM cell have been conducted. Results indicate that the reverse-biased drain region is sensitive to SEU, as well as the gate region. The largest amount of charge collection in device and the lowest LET threshold of SEU in SRAM both occur when the ion strikes at the drain/body junction area and passes through the centre part of the reverse junction.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706475
J.Q. Yang, J.F. Yang, J. Kang, X.Y. Liu, R. Han, P. Kirsch, H. Tseng, R. Jammy
The extended flicker noise measurement incorporating with BTI evaluation is applied to investigate the bulk trapping density Nt in HK/MG stacks and the correlated BTI behaviors. An effective evaluating technique on BTI/TDDB is developed. This method will help to understand the physical original of BTI degradation.
{"title":"Correlation between dielectric traps and BTI characteristics of high-k/ metal gate MOSFETs","authors":"J.Q. Yang, J.F. Yang, J. Kang, X.Y. Liu, R. Han, P. Kirsch, H. Tseng, R. Jammy","doi":"10.1109/IIRW.2010.5706475","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706475","url":null,"abstract":"The extended flicker noise measurement incorporating with BTI evaluation is applied to investigate the bulk trapping density Nt in HK/MG stacks and the correlated BTI behaviors. An effective evaluating technique on BTI/TDDB is developed. This method will help to understand the physical original of BTI degradation.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116357118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706506
R. Wong, P. Su, S. Wen, Brendan Dwyer McNally, S. Coleman
The soft error rate of the wire bonded memory was not affected by the 3000X increase in the Radon concentration. The packaging material and thickness of the molding compound appear to provide a sufficient barrier to minimize Radon diffusion. Ambient Radon levels do not appear to contribute to current soft error rate observed in these devices. Follow up experiments may be completed on flip chip device to determine Radon would diffuse into the flip chip package.
{"title":"The effect of Radon on soft error rates for wire bonded memories","authors":"R. Wong, P. Su, S. Wen, Brendan Dwyer McNally, S. Coleman","doi":"10.1109/IIRW.2010.5706506","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706506","url":null,"abstract":"The soft error rate of the wire bonded memory was not affected by the 3000X increase in the Radon concentration. The packaging material and thickness of the molding compound appear to provide a sufficient barrier to minimize Radon diffusion. Ambient Radon levels do not appear to contribute to current soft error rate observed in these devices. Follow up experiments may be completed on flip chip device to determine Radon would diffuse into the flip chip package.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128479997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706509
P. Chia, Shi-Jie Wen, S. Baeg
This paper proposes a new accelerated HCI reliability stress method specifically targeting DRAM components. The merit of this stress method is to provide the worst case design requirement of the data word access rate.
{"title":"New DRAM HCI qualification method emphasizing on repeated memory access","authors":"P. Chia, Shi-Jie Wen, S. Baeg","doi":"10.1109/IIRW.2010.5706509","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706509","url":null,"abstract":"This paper proposes a new accelerated HCI reliability stress method specifically targeting DRAM components. The merit of this stress method is to provide the worst case design requirement of the data word access rate.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128628848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706482
B. Bittel, T. Pomorski, P. Lenahan, S. King
The electronic properties of thin film low-κ interlayer dielectric (ILD) and etch stop layers (ESL) are important issues in present day ULSI development.1–6 Low-κ ILD and ESLs with dielectric constants significantly less then those of SiO2 and SiN are utilized to reduce capacitance induced RC delays in ULSI circuits. However as the semiconductor industry looks to transition to 16 nm and beyond technology nodes, numerous reliability concerns with low-k materials need to be addressed. In particular, leakage currents, time dependent dielectric breakdown (TDDM) and stress induced leakage currents (SILC) are critical problems that are not yet well understood in ILD. A topic of current interest is ultraviolet light (UV curing) of low-k materials.5,6 We have made electron spin resonance (ESR) and current density versus voltage measurements on a moderately extensive set of dielectric/silicon structures involving materials of importance to low-k interconnect systems. Most of the dielectrics studied involve various compositions of SiOC:H. In addition we have also made measurements on other dielectrics including SiO2, SiCN:H and SiN:H.
{"title":"Defects in low-κ dielectrics and etch stop layers for use as interlayer dielectrics in ULSI","authors":"B. Bittel, T. Pomorski, P. Lenahan, S. King","doi":"10.1109/IIRW.2010.5706482","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706482","url":null,"abstract":"The electronic properties of thin film low-κ interlayer dielectric (ILD) and etch stop layers (ESL) are important issues in present day ULSI development.1–6 Low-κ ILD and ESLs with dielectric constants significantly less then those of SiO2 and SiN are utilized to reduce capacitance induced RC delays in ULSI circuits. However as the semiconductor industry looks to transition to 16 nm and beyond technology nodes, numerous reliability concerns with low-k materials need to be addressed. In particular, leakage currents, time dependent dielectric breakdown (TDDM) and stress induced leakage currents (SILC) are critical problems that are not yet well understood in ILD. A topic of current interest is ultraviolet light (UV curing) of low-k materials.5,6 We have made electron spin resonance (ESR) and current density versus voltage measurements on a moderately extensive set of dielectric/silicon structures involving materials of importance to low-k interconnect systems. Most of the dielectrics studied involve various compositions of SiOC:H. In addition we have also made measurements on other dielectrics including SiO2, SiCN:H and SiN:H.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"13 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113989446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706493
Sung-Rae Kim, K. Han, Kin-Sing Lee, Tae-Hoon Kim, J. Wolfman, Yu Wang, Schmit Ben, Kris Hauch, Hyuk Kim, P. Lee, Eugene Minh, Yingbo Jia, F. Dhaoui, Patty Liu, Huan-Chung Tseng
We observed Single Bit Read Disturb failure in SRAM blocks with embedded Flash process. Such failures are not observed in pure logic process because pure logic process does not require additional thermal budget. In embedded Flash process, static Noise Margin (SNM) and leakage current degrades, causing more Single Bit Failure (SBF) at high VCC and/or high temperature. We optimized SRAM bitcell's transistor size and improved the process leakage. We report the procedure for beta optimization and did standby leakage analysis, which points to the location electrically. After the process fix and bitcell beta increase, the SBF problem was resolved and the product became more reliable with more Static Noise Margin (SNM).
{"title":"Single Bit Read Disturb failure mechanism and transistor size optimization for dual port SRAM bitcell in embedded NVM process SOC applications","authors":"Sung-Rae Kim, K. Han, Kin-Sing Lee, Tae-Hoon Kim, J. Wolfman, Yu Wang, Schmit Ben, Kris Hauch, Hyuk Kim, P. Lee, Eugene Minh, Yingbo Jia, F. Dhaoui, Patty Liu, Huan-Chung Tseng","doi":"10.1109/IIRW.2010.5706493","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706493","url":null,"abstract":"We observed Single Bit Read Disturb failure in SRAM blocks with embedded Flash process. Such failures are not observed in pure logic process because pure logic process does not require additional thermal budget. In embedded Flash process, static Noise Margin (SNM) and leakage current degrades, causing more Single Bit Failure (SBF) at high VCC and/or high temperature. We optimized SRAM bitcell's transistor size and improved the process leakage. We report the procedure for beta optimization and did standby leakage analysis, which points to the location electrically. After the process fix and bitcell beta increase, the SBF problem was resolved and the product became more reliable with more Static Noise Margin (SNM).","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-10-01DOI: 10.1109/IIRW.2010.5706499
Yinghong Zhao, Xu Zeng, Wei Liu, Fan Zhang, Y. K. Lim
The broad time-to-failure distribution and bimodality of downstream electromigration (EM) in 45nm technology node are investigated. Liner void and end of line void at wafer edge on downstream EM structure after M1 CMP is a clear physical vapor deposition (PVD) shadowing effect signature caused by poor liner gap fill capability. Furthermore, void growth study during early electromigration stage effectively indicates that the void is initiated at the bottom corner of the via interfacing with cap layer for early failures and slit void is consistently observed at same location on unstressed sample. These pre-existed voids create poor contact either on via bottom interface or trench and cap layer interface or via bottom corner which produce a difference in failure time resulting in poor time to failure (TTF) spread and lower t50. New Cu seed deposition technique eliminates end of line void and liner void and it turns out to improve downstream EM performance. Optimized post etch treatment (PET) chemicals help to reduce Cu oxidation to improve via bottom integrity and eliminate slit void. This effective post etch treatment was demonstrated to improve downstream EM bimodality behavior to tight mono-modal distribution. Via above to metal below overlay is also one of key factors for downstream EM improvement. There is a strong correlation between the TTF and the via to metal overlay and stringent overlay control is beneficial to improve downstream EM sigma and t50.
{"title":"Downstream electromigration improvement in 45nm technology","authors":"Yinghong Zhao, Xu Zeng, Wei Liu, Fan Zhang, Y. K. Lim","doi":"10.1109/IIRW.2010.5706499","DOIUrl":"https://doi.org/10.1109/IIRW.2010.5706499","url":null,"abstract":"The broad time-to-failure distribution and bimodality of downstream electromigration (EM) in 45nm technology node are investigated. Liner void and end of line void at wafer edge on downstream EM structure after M1 CMP is a clear physical vapor deposition (PVD) shadowing effect signature caused by poor liner gap fill capability. Furthermore, void growth study during early electromigration stage effectively indicates that the void is initiated at the bottom corner of the via interfacing with cap layer for early failures and slit void is consistently observed at same location on unstressed sample. These pre-existed voids create poor contact either on via bottom interface or trench and cap layer interface or via bottom corner which produce a difference in failure time resulting in poor time to failure (TTF) spread and lower t50. New Cu seed deposition technique eliminates end of line void and liner void and it turns out to improve downstream EM performance. Optimized post etch treatment (PET) chemicals help to reduce Cu oxidation to improve via bottom integrity and eliminate slit void. This effective post etch treatment was demonstrated to improve downstream EM bimodality behavior to tight mono-modal distribution. Via above to metal below overlay is also one of key factors for downstream EM improvement. There is a strong correlation between the TTF and the via to metal overlay and stringent overlay control is beneficial to improve downstream EM sigma and t50.","PeriodicalId":332664,"journal":{"name":"2010 IEEE International Integrated Reliability Workshop Final Report","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121914251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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