IEEE International Electron Devices Meeting 2003

Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs

Pub Date : 2003-12-08 DOI: 10.1109/IEDM.2003.1269413 H. Ohtake, M. Tagami, K. Arita, Y. Hayashi

70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory

Pub Date : 2003-12-08 DOI: 10.1109/IEDM.2003.1269405 Y. Yim, Kwang-Shik Shin, S. Hur, Jaeduk Lee, Ihn-Gee Balk, H. Kim, Soo-Jin Chai, Eunkyeong Choi, Mincheol Park, D. Eun, Sungyeon Lee, Hye-Jin Lim, S. Youn, Sungyeon Lee, Tae-Jung Kim, Hansoo Kim, Kyucharn Park, Ki-Nam Kim

Experimental evidence of grain-boundary related hot-carrier degradation mechanism in low-temperature poly-Si thin-film-transistors

Pub Date : 2003-12-08 DOI: 10.1109/IEDM.2003.1269250 T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki, T. Tsuchiya