Y. Yim, Kwang-Shik Shin, S. Hur, Jaeduk Lee, Ihn-Gee Balk, H. Kim, Soo-Jin Chai, Eunkyeong Choi, Mincheol Park, D. Eun, Sungyeon Lee, Hye-Jin Lim, S. Youn, Sungyeon Lee, Tae-Jung Kim, Hansoo Kim, Kyucharn Park, Ki-Nam Kim
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引用次数: 9
Abstract
A 4 Gb NAND flash memory with a 70 nm design rule is developed for mass storage applications. The cell size is 0.025 /spl mu/m/sup 2/, which is the smallest value ever reported. For the integration, an ArF lithography process along with resolution enhancing techniques was utilized, and poly-Si/W gate technology with an optimized re-oxidation process was implemented.
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