Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269413
H. Ohtake, M. Tagami, K. Arita, Y. Hayashi
Misalignment-tolerant, Cu dual damascene interconnects (DDI) are successfully obtained in low-k SiOCH film (k=2.9) by a novel via-first multi-hard-mask (VF-MHM) process without via-poisoning of the photo-resist. In the VF-MHM, the etching sequence has higher misalignment margin between the vias and the upper lines in the Cu DDI as compared with a conventional trench-first one (TF-MHM). The VF-MHM process improves the fabrication yield and TDDB reliability of low-k/Cu-DDIs, and is a key scheme for sub-100 nm-node, ASIC fabrication.
在低k SiOCH薄膜(k=2.9)中，通过一种新型的先过孔多硬掩膜(VF-MHM)工艺，成功地获得了Cu双damascene互连(DDI)，并且没有光致抗蚀剂的过孔中毒。在VF-MHM中，与传统的沟槽优先蚀刻(TF-MHM)相比，在Cu DDI中过孔和上线之间的蚀刻顺序具有更高的偏差裕度。VF-MHM工艺提高了低k/ cu - ddi的成品率和TDDB可靠性，是100纳米以下节点ASIC制造的关键方案。
{"title":"Misalignment-tolerated, Cu dual damascene interconnects with low-k SiOCH film by a novel via-first, multi-hard-mask process for sub-100nm-node, ASICs","authors":"H. Ohtake, M. Tagami, K. Arita, Y. Hayashi","doi":"10.1109/IEDM.2003.1269413","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269413","url":null,"abstract":"Misalignment-tolerant, Cu dual damascene interconnects (DDI) are successfully obtained in low-k SiOCH film (k=2.9) by a novel via-first multi-hard-mask (VF-MHM) process without via-poisoning of the photo-resist. In the VF-MHM, the etching sequence has higher misalignment margin between the vias and the upper lines in the Cu DDI as compared with a conventional trench-first one (TF-MHM). The VF-MHM process improves the fabrication yield and TDDB reliability of low-k/Cu-DDIs, and is a key scheme for sub-100 nm-node, ASIC fabrication.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115665708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269405
Y. Yim, Kwang-Shik Shin, S. Hur, Jaeduk Lee, Ihn-Gee Balk, H. Kim, Soo-Jin Chai, Eunkyeong Choi, Mincheol Park, D. Eun, Sungyeon Lee, Hye-Jin Lim, S. Youn, Sungyeon Lee, Tae-Jung Kim, Hansoo Kim, Kyucharn Park, Ki-Nam Kim
A 4 Gb NAND flash memory with a 70 nm design rule is developed for mass storage applications. The cell size is 0.025 /spl mu/m/sup 2/, which is the smallest value ever reported. For the integration, an ArF lithography process along with resolution enhancing techniques was utilized, and poly-Si/W gate technology with an optimized re-oxidation process was implemented.
{"title":"70nm NAND flash technology with 0.025 /spl mu/m/sup 2/ cell size for 4Gb flash memory","authors":"Y. Yim, Kwang-Shik Shin, S. Hur, Jaeduk Lee, Ihn-Gee Balk, H. Kim, Soo-Jin Chai, Eunkyeong Choi, Mincheol Park, D. Eun, Sungyeon Lee, Hye-Jin Lim, S. Youn, Sungyeon Lee, Tae-Jung Kim, Hansoo Kim, Kyucharn Park, Ki-Nam Kim","doi":"10.1109/IEDM.2003.1269405","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269405","url":null,"abstract":"A 4 Gb NAND flash memory with a 70 nm design rule is developed for mass storage applications. The cell size is 0.025 /spl mu/m/sup 2/, which is the smallest value ever reported. For the integration, an ArF lithography process along with resolution enhancing techniques was utilized, and poly-Si/W gate technology with an optimized re-oxidation process was implemented.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116694085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269250
T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki, T. Tsuchiya
Unique degradation behavior in the transfer characteristics was observed in low-temperature (LT) polycrystalline silicon (poly-Si) thin-film-transistors (TFTs) after hot carrier stress. To understand the degradation mechanism, stress-induced-resistance R/sub l/ is introduced, which is connected with channel resistance R/sub channel/ in series. A possible origin of R/sub l/ is potential barriers caused by negative charges generated at grain boundaries. Furthermore, using devices with a different density of grain boundary, the grain-boundary related degradation mechanism is experimentally demonstrated. Reducing the grain boundary density is effective for improving the hot carrier reliability.
{"title":"Experimental evidence of grain-boundary related hot-carrier degradation mechanism in low-temperature poly-Si thin-film-transistors","authors":"T. Yoshida, K. Yoshino, M. Takei, A. Hara, N. Sasaki, T. Tsuchiya","doi":"10.1109/IEDM.2003.1269250","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269250","url":null,"abstract":"Unique degradation behavior in the transfer characteristics was observed in low-temperature (LT) polycrystalline silicon (poly-Si) thin-film-transistors (TFTs) after hot carrier stress. To understand the degradation mechanism, stress-induced-resistance R/sub l/ is introduced, which is connected with channel resistance R/sub channel/ in series. A possible origin of R/sub l/ is potential barriers caused by negative charges generated at grain boundaries. Furthermore, using devices with a different density of grain boundary, the grain-boundary related degradation mechanism is experimentally demonstrated. Reducing the grain boundary density is effective for improving the hot carrier reliability.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127513626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269312
M. Kumar, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, K. Bard, D. Dobuzinsky, P. McFarland, C. Schiller, B. Messenger, S. E. Rathmill, A. Gasasira, P. Parries, S. Iyer, S. Chaloux, H. Ho
This paper, for the first time, reports a fully-functional 130 nm trench-based eDRAM (embedded DRAM), built in unpatterned SOI. The functionality of the eDRAM is shown by the test results of: (a) 524 Kb ADM (array diagnostic monitors) macros and (b) 16 Mb product macros. The eDRAM functionality is enabled by using low-leakage floating-body array pass transistors. The support logic circuitry of the eDRAM is built using IBM's high-performance 130 nm SOI logic process technology. Wafer fixable yield as high as 67% has been obtained for 524 Kb ADMs. In addition, 16 Mb product macros were built and found to be fully fixable, exhibiting retention time on the order of 80 ms. This technology allows a simple and low-cost integration of trench-based eDRAM with high-performance SOI logic for system-on-a-chip (SoC) applications.
{"title":"A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications","authors":"M. Kumar, M. Steigerwalt, B. Walsh, T.L. Doney, D. Wildrick, K. Bard, D. Dobuzinsky, P. McFarland, C. Schiller, B. Messenger, S. E. Rathmill, A. Gasasira, P. Parries, S. Iyer, S. Chaloux, H. Ho","doi":"10.1109/IEDM.2003.1269312","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269312","url":null,"abstract":"This paper, for the first time, reports a fully-functional 130 nm trench-based eDRAM (embedded DRAM), built in unpatterned SOI. The functionality of the eDRAM is shown by the test results of: (a) 524 Kb ADM (array diagnostic monitors) macros and (b) 16 Mb product macros. The eDRAM functionality is enabled by using low-leakage floating-body array pass transistors. The support logic circuitry of the eDRAM is built using IBM's high-performance 130 nm SOI logic process technology. Wafer fixable yield as high as 67% has been obtained for 524 Kb ADMs. In addition, 16 Mb product macros were built and found to be fully fixable, exhibiting retention time on the order of 80 ms. This technology allows a simple and low-cost integration of trench-based eDRAM with high-performance SOI logic for system-on-a-chip (SoC) applications.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125045236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269350
H. Ishida, Y. Hirose, T. Murata, A. Kanda, Y. Ikeda, T. Matsuno, K. Inoue, Y. Uemoto, T. Tanaka, T. Egawa, D. Ueda
An extremely high power Tx/Rx switch IC based on AlGaN/GaN HFETs has been developed for the first time. A low on-state resistance realized by Si doping techniques and a low off-state capacitance by using an Al/sub 2/O/sub 3/ substrate led to excellent performance of 0.26 dB insertion loss and 27 dB isolation with the power handling capability of 43 W at 1 GHz.
{"title":"A high power Tx/Rx switch IC using AlGaN/GaN HFETs","authors":"H. Ishida, Y. Hirose, T. Murata, A. Kanda, Y. Ikeda, T. Matsuno, K. Inoue, Y. Uemoto, T. Tanaka, T. Egawa, D. Ueda","doi":"10.1109/IEDM.2003.1269350","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269350","url":null,"abstract":"An extremely high power Tx/Rx switch IC based on AlGaN/GaN HFETs has been developed for the first time. A low on-state resistance realized by Si doping techniques and a low off-state capacitance by using an Al/sub 2/O/sub 3/ substrate led to excellent performance of 0.26 dB insertion loss and 27 dB isolation with the power handling capability of 43 W at 1 GHz.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"50 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123396938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269429
A. Oates
High-k gate dielectric materials are likely to be implemented in Si CMOS processes in the near future. Reliability characteristics that closely match, or exceed, those of SiO/sub 2/ will be one of the primary goals of future development work. In this paper we review the status of reliability studies of high-k gate dielectrics. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fixed charge. The reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. Attainment of reliability goals will require elimination of charging effects, which dominate transistor degradation.
{"title":"Reliability issues for high-k gate dielectrics","authors":"A. Oates","doi":"10.1109/IEDM.2003.1269429","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269429","url":null,"abstract":"High-k gate dielectric materials are likely to be implemented in Si CMOS processes in the near future. Reliability characteristics that closely match, or exceed, those of SiO/sub 2/ will be one of the primary goals of future development work. In this paper we review the status of reliability studies of high-k gate dielectrics. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fixed charge. The reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. Attainment of reliability goals will require elimination of charging effects, which dominate transistor degradation.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125467664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269425
Yi-Chou Chen, Chun-Fu Chen, C. T. Chen, J. Yu, S. Wu, S. Lung, Rich Liu, Chih-Yuan Lu
A new concept for non-volatile memory is demonstrated. This new technique controls the threshold voltage of the chalcogenide storage device by varying the height and duration of the write pulse. Consequently, the chalcogenide device serves as both the access element and the memory element. Therefore, it does not need any access transistor in the memory array. The new memory achieves the requirement of non-volatility, fast writing/reading, random access, high scalability, compact cell size, and low cost.
{"title":"An access-transistor-free (0T/1R) non-volatile resistance random access memory (RRAM) using a novel threshold switching, self-rectifying chalcogenide device","authors":"Yi-Chou Chen, Chun-Fu Chen, C. T. Chen, J. Yu, S. Wu, S. Lung, Rich Liu, Chih-Yuan Lu","doi":"10.1109/IEDM.2003.1269425","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269425","url":null,"abstract":"A new concept for non-volatile memory is demonstrated. This new technique controls the threshold voltage of the chalcogenide storage device by varying the height and duration of the write pulse. Consequently, the chalcogenide device serves as both the access element and the memory element. Therefore, it does not need any access transistor in the memory array. The new memory achieves the requirement of non-volatility, fast writing/reading, random access, high scalability, compact cell size, and low cost.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126618711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269322
L. Lucci, D. Esseni, J. Loo, Y. Ponomarev, L. Selmi, A. Abramo, E. Sangiorgi
In this paper, we report measurements of electron effective mobility (/spl mu//sub eff/) in ultra-thin (UT) pure SiO/sub 2/ bulk MOSFETs. A low substrate doping was intentionally used to better detect a possible /spl mu//sub eff/ degradation at small T/sub ox/. New quantitative criteria were developed and used to obtain /spl mu//sub eff/ measurements unaffected by either gate doping penetration or gate oxide leakage. Mobility simulations, based on an improved and comprehensive remote Coulomb scattering (RCS) model, exhibit a good agreement with the experimentally observed mobility reduction at small T/sub ox/. Our results indicate that polysilicon screening is an essential ingredient to reconcile the RCS models with the experiments.
{"title":"Quantitative assessment of mobility degradation by remote Coulomb scattering in ultra-thin oxide MOSFETs: measurements and simulations","authors":"L. Lucci, D. Esseni, J. Loo, Y. Ponomarev, L. Selmi, A. Abramo, E. Sangiorgi","doi":"10.1109/IEDM.2003.1269322","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269322","url":null,"abstract":"In this paper, we report measurements of electron effective mobility (/spl mu//sub eff/) in ultra-thin (UT) pure SiO/sub 2/ bulk MOSFETs. A low substrate doping was intentionally used to better detect a possible /spl mu//sub eff/ degradation at small T/sub ox/. New quantitative criteria were developed and used to obtain /spl mu//sub eff/ measurements unaffected by either gate doping penetration or gate oxide leakage. Mobility simulations, based on an improved and comprehensive remote Coulomb scattering (RCS) model, exhibit a good agreement with the experimentally observed mobility reduction at small T/sub ox/. Our results indicate that polysilicon screening is an essential ingredient to reconcile the RCS models with the experiments.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122396240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269332
G. Boselli, J. Rodriguez, C. Duvvury, V. Reddy, P. Chidambaram, B. Hornung
A new phenomenon, reported in this paper for the first time, produces a dramatic reduction of the nMOS and pMOS triggering voltage (V/sub Tl/) under ESD conditions for an ultra-scaled 90 nm CMOS technology used in high performance applications. This V/sub Tl/ reduction is caused by the merging of pocket implants in short gate length transistors. This has a serious impact on the ESD sensitivity of output drivers, placing restrictions on the design of effective protection devices and burn-in voltage during product screening.
{"title":"Technology scaling effects on the ESD design parameters in sub-100 nm CMOS transistors","authors":"G. Boselli, J. Rodriguez, C. Duvvury, V. Reddy, P. Chidambaram, B. Hornung","doi":"10.1109/IEDM.2003.1269332","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269332","url":null,"abstract":"A new phenomenon, reported in this paper for the first time, produces a dramatic reduction of the nMOS and pMOS triggering voltage (V/sub Tl/) under ESD conditions for an ultra-scaled 90 nm CMOS technology used in high performance applications. This V/sub Tl/ reduction is caused by the merging of pocket implants in short gate length transistors. This has a serious impact on the ESD sensitivity of output drivers, placing restrictions on the design of effective protection devices and burn-in voltage during product screening.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"111 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-12-08DOI: 10.1109/IEDM.2003.1269406
Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa
The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.
开发了第一个真正的2- f /sup 2//bit闪存单元，编程吞吐量为10 MB/s。在该单元中，辅助门与型闪存的扩散层局部位线被辅助门下的反转层位线所取代。位线间距因此减少到2f。采用一种新的无扩散层技术制备了一种无漏失干扰、无软写的闪存电池。源端注入编程适用于新的闪存单元;因此，单元编程时间减少到1 /spl mu/s。迄今为止，最小的存储单元(0.0162 /spl mu/m/sup 2//bit)是通过采用90nm技术节点和多级存储单元技术实现的。
{"title":"90-nm-node multi-level AG-AND type flash memory with cell size of true 2 F/sup 2//bit and programming throughput of 10 MB/s","authors":"Y. Sasago, H. Kurata, T. Arigane, K. Otsuga, T. Kobayashi, Y. Ikeda, T. Fukumura, S. Narumi, A. Sato, T. Terauchi, M. Shimizu, S. Noda, K. Kozakai, O. Tsuchiya, K. Furusawa","doi":"10.1109/IEDM.2003.1269406","DOIUrl":"https://doi.org/10.1109/IEDM.2003.1269406","url":null,"abstract":"The first true 2-F/sup 2//bit flash cell with a programming throughput of 10 MB/s was developed. In this cell, diffusion-layer local bit lines of an assist-gate AND-type flash are replaced by inversion-layer ones under assist gates. The bit-line pitch is thus reduced to 2 F. A drain-disturbance-free and soft-write-free flash cell was produced by means of a new diffusion-layer-less technology. Source-side injection programming is applicable to the new flash cell; therefore, the cell programming time is reduced to 1 /spl mu/s. The smallest memory cell (0.0162 /spl mu/m/sup 2//bit) achieved to date was accomplished by using a 90-nm technology node and applying multi-level cell technology.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130574572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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