2018 IEEE Symposium on VLSI Technology

A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs

Pub Date : 2018-06-18 DOI: 10.1109/VLSIT.2018.8510622 K. Ni, M. Jerry, Jeffrey A. Smith, S. Datta

Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond

Pub Date : 2018-06-18 DOI: 10.1109/VLSIT.2018.8510653 C. Park, H. Lee, C. Ching, J. Ahn, R. Wang, M. Pakala, S. H. Kang

A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications

Pub Date : 2018-06-18 DOI: 10.1109/VLSIT.2018.8510679 M. Jerry, A. Aziz, K. Ni, S. Datta, S. Gupta, N. Shukla