Pub Date : 2018-06-18DOI: 10.1109/VLSIT.2018.8510622
K. Ni, M. Jerry, Jeffrey A. Smith, S. Datta
In this work we develop a compact model of ferroelectric field-effect-transistors (FeFET) for memory applications, enabling their exploration at the circuit and architecture level. In contrast to Landau-Khalatnikov (L-K) based approaches, the presented model is founded on the combination of a nucleation dominated multi-domain Presiach theory of ferroelectric switching with a conventional transistor model. The model successfully reproduces the evolution of the FeFET memory window as a function of the program and erase conditions (amplitude, pulse width, and history). To calibrate the model, we fabricated 10nm thick Hf0.4Zr0.6O2 (HZO) MFM capacitors and FeFETs and characterized the polarization switching dynamics. Our results highlight the importance of accounting for the switching history, minor loop trajectory, and coupled time-voltage response of the ferroelectric to quantitatively reproduce the measured FeFET characteristics.
{"title":"A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs","authors":"K. Ni, M. Jerry, Jeffrey A. Smith, S. Datta","doi":"10.1109/VLSIT.2018.8510622","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510622","url":null,"abstract":"In this work we develop a compact model of ferroelectric field-effect-transistors (FeFET) for memory applications, enabling their exploration at the circuit and architecture level. In contrast to Landau-Khalatnikov (L-K) based approaches, the presented model is founded on the combination of a nucleation dominated multi-domain Presiach theory of ferroelectric switching with a conventional transistor model. The model successfully reproduces the evolution of the FeFET memory window as a function of the program and erase conditions (amplitude, pulse width, and history). To calibrate the model, we fabricated 10nm thick Hf0.4Zr0.6O2 (HZO) MFM capacitors and FeFETs and characterized the polarization switching dynamics. Our results highlight the importance of accounting for the switching history, minor loop trajectory, and coupled time-voltage response of the ferroelectric to quantitatively reproduce the measured FeFET characteristics.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"44 1","pages":"131-132"},"PeriodicalIF":0.0,"publicationDate":"2018-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83717164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-18DOI: 10.1109/VLSIT.2018.8510653
C. Park, H. Lee, C. Ching, J. Ahn, R. Wang, M. Pakala, S. H. Kang
The scaling of STT-MRAM for deeply scaled nodes (e.g. sub-10 nm CMOS) requires low resistance-area-product (RA) magnetic tunnel junctions (MTJs) to contain switching voltage (Vc) and to assure high endurance. In contrast to various reports, we demonstrate systematic engineering of low-RA MTJs without trading off key device attributes and remarkably, with higher barrier reliability. The MTJs integrate an ultra-thin synthetic antiferromagnetic layer (tSAF) with a Co/Pt pseudo-alloy pinned layer. By reducing RA from 10 to 5 Ωµm2, significantly reduced Vc and reliable switching at 5 ns have been achieved. Furthermore, the breakdown voltage (VBD) has been improved. The results suggest that the tunability of MTJ is extended to sub-10 nm CMOS for high-performance and high-reliability MRAM.
{"title":"Low RA Magnetic Tunnel Junction Arrays in Conjunction with Low Switching Current and High Breakdown Voltage for STT-MRAM at 10 nm and Beyond","authors":"C. Park, H. Lee, C. Ching, J. Ahn, R. Wang, M. Pakala, S. H. Kang","doi":"10.1109/VLSIT.2018.8510653","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510653","url":null,"abstract":"The scaling of STT-MRAM for deeply scaled nodes (e.g. sub-10 nm CMOS) requires low resistance-area-product (RA) magnetic tunnel junctions (MTJs) to contain switching voltage (Vc) and to assure high endurance. In contrast to various reports, we demonstrate systematic engineering of low-RA MTJs without trading off key device attributes and remarkably, with higher barrier reliability. The MTJs integrate an ultra-thin synthetic antiferromagnetic layer (tSAF) with a Co/Pt pseudo-alloy pinned layer. By reducing RA from 10 to 5 Ωµm2, significantly reduced Vc and reliable switching at 5 ns have been achieved. Furthermore, the breakdown voltage (VBD) has been improved. The results suggest that the tunability of MTJ is extended to sub-10 nm CMOS for high-performance and high-reliability MRAM.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"25 1","pages":"185-186"},"PeriodicalIF":0.0,"publicationDate":"2018-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80044131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-18DOI: 10.1109/VLSIT.2018.8510679
M. Jerry, A. Aziz, K. Ni, S. Datta, S. Gupta, N. Shukla
In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO2 to overcome the fundamental trade-off between memory window MW /read current ratio (Iread,1/Iread,0) , and program voltage (Vprog)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (ION/IOFF >107) – during read, the TS turns ON only if the FeFET is in the low-VT SET state, and remains OFF if the FeFET is in the high-VT RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger Iread,1/Iread,0 compared to the FeFET, at iso-Vprog (DC); (b) Enables 25% reduction in Vprog at iso-Iread,1/Iread,0 during pulse operation-facilitated by the 8× improvement in Iread,1/Iread,0; (c) Exhibits 2.5×reduction in programming power at iso-Iread,1/Iread,0 in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.
{"title":"A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications","authors":"M. Jerry, A. Aziz, K. Ni, S. Datta, S. Gupta, N. Shukla","doi":"10.1109/VLSIT.2018.8510679","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510679","url":null,"abstract":"In this work, we demonstrate a novel Hybrid-FeFET (H-FeFET) that leverages the threshold switching characteristics of Ag/HfO<inf>2</inf> to overcome the fundamental trade-off between memory window MW /read current ratio (I<inf>read,1</inf>/I<inf>read,0</inf>) , and program voltage (V<inf>prog</inf>)/maximum electric-field in standard FeFETs for non-volatile memory application. The H-FeFET incorporates the threshold switch (TS) in the source of the FeFET, and is designed to exhibit a ferroelectric state-dependent volatile HRS to LRS transition (I<inf>ON</inf>/I<inf>OFF</inf> >10<sup>7</sup>) – during read, the TS turns ON only if the FeFET is in the low-V<inf>T</inf> SET state, and remains OFF if the FeFET is in the high-V<inf>T</inf> RESET state, thus, selectively suppressing the RESET read current. Leveraging this principle, the H-FeFET: a Demonstrates 77% higher MW and 1000× larger I<inf>read,1</inf>/I<inf>read,0</inf> compared to the FeFET, at iso-V<inf>prog</inf> (DC); (b) Enables 25% reduction in V<inf>prog</inf> at iso-I<inf>read,1</inf>/I<inf>read,0</inf> during pulse operation-facilitated by the 8× improvement in I<inf>read,1</inf>/I<inf>read,0</inf>; (c) Exhibits 2.5×reduction in programming power at iso-I<inf>read,1</inf>/I<inf>read,0</inf> in the H-FeFET-based AND array architecture, as shown by simulations. Thus, the H-FeFET overcomes the FeFET design challenges while retaining its existing advantages, making it a promising candidate for nonvolatile memory applications.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"24 1","pages":"129-130"},"PeriodicalIF":0.0,"publicationDate":"2018-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89894588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510646
K. Jo, W. Kim, M. Takenaka, S. Takagi
We demonstrate high performance extremely-thin-body (ETB) Ge-on-insulator (GOI) and SiGe-on-insulator (SGOI) pMOSFETs with the body thickness ranging from 10 to 2 nm by applying the improved Ge condensation process with slow cooling to initial substrates with thinner SiGe layers. When we employ Si/40-nm-thin Si0.75Ge0.25/SOI structures as starting substrates for Ge condensation, the high compressive strain of ~1.75% is maintained in GOI, leading to the operation of 10-nm-thick GOI pMOSFETs with hole mobility (µh) of 467 cm2/Vs. Furthermore, by thinning the fabricated GOI and SGOI films, we demonstrate the operation of ETB GOI and SGOI pMOSFETs with the body thickness down to 2 nm without losing high compressive strain. Comparing with the reported results, the record-high µh is obtained in GOI pMOSFETs in the GOI thickness ranging from 10 to 2 nm.
{"title":"Hole mobility enhancement in extremely-thin-body strained GOI and SGOI pMOSFETs by improved Ge condensation method","authors":"K. Jo, W. Kim, M. Takenaka, S. Takagi","doi":"10.1109/VLSIT.2018.8510646","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510646","url":null,"abstract":"We demonstrate high performance extremely-thin-body (ETB) Ge-on-insulator (GOI) and SiGe-on-insulator (SGOI) pMOSFETs with the body thickness ranging from 10 to 2 nm by applying the improved Ge condensation process with slow cooling to initial substrates with thinner SiGe layers. When we employ Si/40-nm-thin Si0.75Ge0.25/SOI structures as starting substrates for Ge condensation, the high compressive strain of ~1.75% is maintained in GOI, leading to the operation of 10-nm-thick GOI pMOSFETs with hole mobility (µh) of 467 cm2/Vs. Furthermore, by thinning the fabricated GOI and SGOI films, we demonstrate the operation of ETB GOI and SGOI pMOSFETs with the body thickness down to 2 nm without losing high compressive strain. Comparing with the reported results, the record-high µh is obtained in GOI pMOSFETs in the GOI thickness ranging from 10 to 2 nm.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"55 1","pages":"195-196"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74035864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510632
H. Lo, D. Choi, Y. Hu, Y. Shen, Y. Qi, J. Peng, D. Zhou, M. Mohan, C. Yong, H. Zhan, H. Wei, X. He, D. Kang, A. Sirman, Y. Wang, H. Zang, S. Mun, A. Vinslava, W.H. Chen, C. Gaire, J. Liu, X. Dou, Y. Shi, P. Zhao, B. Zhu, A. Jha, X. Zhang, X. Wan, E. Lavigne, C. Kyono, M. Togo, J. Versaggi, H. Yu, O. Hu, J. lee, S. Samavedam, D. K. Sohn
We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.
{"title":"A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications","authors":"H. Lo, D. Choi, Y. Hu, Y. Shen, Y. Qi, J. Peng, D. Zhou, M. Mohan, C. Yong, H. Zhan, H. Wei, X. He, D. Kang, A. Sirman, Y. Wang, H. Zang, S. Mun, A. Vinslava, W.H. Chen, C. Gaire, J. Liu, X. Dou, Y. Shi, P. Zhao, B. Zhu, A. Jha, X. Zhang, X. Wan, E. Lavigne, C. Kyono, M. Togo, J. Versaggi, H. Yu, O. Hu, J. lee, S. Samavedam, D. K. Sohn","doi":"10.1109/VLSIT.2018.8510632","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510632","url":null,"abstract":"We present a state-of-art 12LP FinFET technology with PPA (Performance, Power, and Area) improvement over 14LPP. 12LP enables >10% area reduction including a 7.5T library and 16% power reduction at fixed frequency or a 15% performance improvement at given leakage over 14LPP with comparable reliability and yield. In addition, SRAMs benefit from a 30% leakage reduction at the same Iread. 12LP extends the 14nm technology with compelling performance and area scaling.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"103 1","pages":"215-216"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77697695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510628
B. Obradovic, T. Rakshit, R. Hatcher, J. Kittl, M. Rodder
We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching. No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present only when significant polarization changes occur. The technological implications of this finding are investigated, and it is found that NCFETs are most likely not suitable for high-performance CMOS logic, due to voltage, frequency, and voltage polarity limitations.
{"title":"Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs","authors":"B. Obradovic, T. Rakshit, R. Hatcher, J. Kittl, M. Rodder","doi":"10.1109/VLSIT.2018.8510628","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510628","url":null,"abstract":"We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching. No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present only when significant polarization changes occur. The technological implications of this finding are investigated, and it is found that NCFETs are most likely not suitable for high-performance CMOS logic, due to voltage, frequency, and voltage polarity limitations.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"62 1","pages":"51-52"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77708311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510636
F. Andrieu, L. Pirro, R. Berthelon, J. Morgan, G. Cibrario, M. Wiatr, J. Hoentschel, M. Vinet
We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (VT-flavors) within a cell. It is successfully applied with nMOS Low-VT (LVT) and pMOS Super-Low-VT (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the VT of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and VDD=0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at VDD=0.4V and FBB=1.6V and improves the energy efficiency with a −13% minimum Energy Delay Product (EDP) along with a 50mV VDD reduction at the minimum EDP.
{"title":"Design Technology Co-Optimization in advanced FDSOI CMOS around the Minimum Energy Point: body biasing and within-cell VT-mixing","authors":"F. Andrieu, L. Pirro, R. Berthelon, J. Morgan, G. Cibrario, M. Wiatr, J. Hoentschel, M. Vinet","doi":"10.1109/VLSIT.2018.8510636","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510636","url":null,"abstract":"We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (VT-flavors) within a cell. It is successfully applied with nMOS Low-VT (LVT) and pMOS Super-Low-VT (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the VT of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and VDD=0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at VDD=0.4V and FBB=1.6V and improves the energy efficiency with a −13% minimum Energy Delay Product (EDP) along with a 50mV VDD reduction at the minimum EDP.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"191 1","pages":"153-154"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77739269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510693
D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong
We report the first GeSn p-FinFETs with sub-10 nm fin width (WFin) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (LCH) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high Gm,int of 900 μS/µm (VDS of -0.5 V) and Gm,int/Ssat of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µeff of 275 cm2/V•s (at inversion carrier density Ninv of 8×1012 cm-2) was also obtained.
{"title":"GeSn p-FinFETs with Sub-10 nm Fin Width Realized on a 200 mm GeSnOI Substrate: Lowest SS of 63 mV/decade, Highest Gm,int of 900 µS/µm, and High-Field µeff of 275 cm2/V•s","authors":"D. Lei, Kaizhen Han, K. Lee, Yi-Chiau Huang, Wei Wang, S. Yadav, Annie Kumar, Ying Wu, Huiquan Heliu, Shengqiang Xu, Yuye Kang, Yang Li, E. Kong, C. S. Tan, X. Gong","doi":"10.1109/VLSIT.2018.8510693","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510693","url":null,"abstract":"We report the first GeSn p-FinFETs with sub-10 nm fin width (W<inf>Fin</inf>) enabled by the formation of the first 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control of the fin dimension, achieving a fin with a top width of 5 nm. Owing to the excellent gate control using extremely scaled GeSn fin and the good GeSn fin quality maintained using a device fabrication process with low thermal budget, an SS of 63 mV/decade was achieved at channel length (L<inf>CH</inf>) of 50 nm, which is a record low for Ge-based p-FETs. Furthermore, record high G<inf>m,int</inf> of 900 μS/µm (V<inf>DS</inf> of -0.5 V) and G<inf>m,int</inf>/S<inf>sat</inf> of 10.5 for GeSn p-FETs were achieved. A high high-field hole mobility µ<inf>eff</inf> of 275 cm<sup>2</sup>/V•s (at inversion carrier density N<inf>inv</inf> of 8×10<sup>12</sup> cm<sup>-2</sup>) was also obtained.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"46 1","pages":"197-198"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81000746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510694
H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon
11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.
{"title":"Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications","authors":"H. Kim, B.H. Choi, Y. Lee, J. Ahn, Y. Bang, Y.D. Lim, J. Do, J.H. Jung, T. Song, Y. Yasuda-Masuoka, K. Park, S. Kwon, J. Yoon","doi":"10.1109/VLSIT.2018.8510694","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510694","url":null,"abstract":"11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated design rules for optimal design kit support with 6.75T library. Compared to 14nm 1st generation FinFET, device performance has been improved by 25% in ring oscillator AC frequency at same Iddq or 42% power reduction is achieved. Adopting already mature 14nm and 10nm process technology, we can setup and demonstrate fast yield ramp.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"213-214"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85429872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-06-01DOI: 10.1109/VLSIT.2018.8510682
W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang
7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um2 is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.
{"title":"True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break","authors":"W. Jeong, S. Maeda, H. Lee, Kw. Lee, T.J. Lee, D. Park, Bs Kim, J. Do, T. Fukai, DJ Kwon, KJ Nam, WJ Rim, Minsik Jang, H.T. Kim, YW Lee, Js Park, Ec Lee, DW Ha, C. Park, H. Cho, S.-M. Jung, H. Kang","doi":"10.1109/VLSIT.2018.8510682","DOIUrl":"https://doi.org/10.1109/VLSIT.2018.8510682","url":null,"abstract":"7nm platform technology that takes full advantage of EUV lithography was developed, where EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means for cutting of SADP/SAQP. The combination of 27nm fin pitch (FP) and 54nm contacted poly pitch (CPP) as well as the high density SRAM cell size of 0.0262 um2 is the smallest in the reported FinFET platform. Further scaling is secured with special constructs and the 3rd generation single diffusion break. Full working of 256M bit SRAM and large-scale logic test chip was demonstrated with guaranteed reliability.","PeriodicalId":6561,"journal":{"name":"2018 IEEE Symposium on VLSI Technology","volume":"61 2 1","pages":"59-60"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77909877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：