10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET

Daniel Gruber, M. Clara, R. Sanchez-Perez, Yu-shan Wang, C. Duller, Gerald Rauter, Patrick Torta, K. Azadet
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引用次数: 2

Abstract

Future multi-band software-defined-radio base-stations for digital beamforming and massive MIMO applications depend heavily on the availability of highly linear and compact data converters with good power efficiency, while at the same time offering multi-GHz signal-bandwidth at sampling rates well in excess of 10GS/s. Wideband RF-sampling D/A-converters have traditionally been implemented in current-steering architectures, mostly with extensive calibration infrastructure [1] –[3]. The transistor stack required to achieve the necessary static and dynamic output impedance for the code-steered current sources leads to limited supply voltage scalability, while the capacitive self-loading by the current-source array makes true wideband matching at the RF-output inherently difficult. Capacitive digital-to-analog converters (C-DAC) have been widely used as RF DAC or switched-capacitor power amplifiers. Up to now digital transmitters have used C-DACs with inherent mixing functionality in polar or IQ systems for synthesis of high-power RF signals of moderate bandwidth of up to 160MHz [4] –[6]. This work uses a capacitive DAC as a direct RF-sampling DAC with moderate output power level for direct signal synthesis over a bandwidth from 0.5GHz up to at least 8GHz.
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10.6基于16nm FinFET片上传输在线匹配网络的多频带软无线电基站应用的12b 16GS/s射频采样电容式DAC
未来用于数字波束形成和大规模MIMO应用的多频带软件定义无线电基站在很大程度上依赖于具有良好功率效率的高线性和紧凑数据转换器的可用性,同时在采样率超过10GS/s的情况下提供多ghz信号带宽。宽带射频采样D/ a转换器传统上是在电流转向架构中实现的,大多数具有广泛的校准基础设施[1]-[3]。为实现代码控制电流源所需的静态和动态输出阻抗所需的晶体管堆栈导致电源电压的可扩展性有限,而电流源阵列的电容性自负载使得rf输出的真正宽带匹配本身就很困难。电容式数模转换器(C-DAC)广泛应用于射频数模转换器或开关电容功率放大器。到目前为止,数字发射机已经在极性或IQ系统中使用具有固有混音功能的c - dac来合成中等带宽高达160MHz[4] -[6]的大功率RF信号。这项工作使用电容式DAC作为直接rf采样DAC,具有中等输出功率水平,可在0.5GHz至至少8GHz的带宽范围内进行直接信号合成。
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10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology 8.1 A 224Gb/s DAC-Based PAM-4 Transmitter with 8-Tap FFE in 10nm CMOS 14.7 An Adaptive Analog Temperature-Healing Low-Power 17.7-to-19.2GHz RX Front-End with ±0.005dB/°C Gain Variation, <1.6dB NF Variation, and <2.2dB IP1dB Variation across -15 to 85°C for Phased-Array Receiver ISSCC 2021 Index to Authors
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