Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365754
Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu
Recently, both the number of smart devices and the amount of data transfered to and from these devices have grown at unprecedented rates. To provide users with a highquality experience, wireless LAN plays a key role among various wireless standards. Wi-Fi 6E extends the available bandwidth, enhances spectral efficiency, increases data rate, and serves more users simultaneously in public areas. To support 1024-QAM in bandwidths up to 160MHz while maintaining sufficient EVM, the ADC has to achieve inband DR of 63-70dB over 80MHz baseband bandwidth. SAR ADCs are used extensively in Wi-Fi receivers due to their low power consumption and small area. But for DR >60 dB, quantization noise and comparator noise become the dominant noise sources. Noise shaping embedded within a SAR ADC has been utilized to suppress these noise sources with minimal overhead [1]–[2]. The maximum reported conversion rate of 10 to 12b 1b/step SAR ADCs is $sim 400$ MS/s, and hence the available bandwidth is limited to 50MHz given an OSR of 4-6. The NS pipeline-SAR ADC [3] was introduced to overcome this limitation by virtue of its superior speed, but at the cost of an active amplifier and calibration. To enlarge the bandwidth and increase the SNR of a SAR ADC, a timeinterleaved noise-shaping SAR (TINS-SAR) architecture is a promising solution [4]. This work presents a passive TI noise-shaping technique to enable a power-efficient, PVT-robust ADC for 80MHz BW and 70dB DR.
{"title":"An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process","authors":"Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu","doi":"10.1109/ISSCC42613.2021.9365754","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365754","url":null,"abstract":"Recently, both the number of smart devices and the amount of data transfered to and from these devices have grown at unprecedented rates. To provide users with a highquality experience, wireless LAN plays a key role among various wireless standards. Wi-Fi 6E extends the available bandwidth, enhances spectral efficiency, increases data rate, and serves more users simultaneously in public areas. To support 1024-QAM in bandwidths up to 160MHz while maintaining sufficient EVM, the ADC has to achieve inband DR of 63-70dB over 80MHz baseband bandwidth. SAR ADCs are used extensively in Wi-Fi receivers due to their low power consumption and small area. But for DR >60 dB, quantization noise and comparator noise become the dominant noise sources. Noise shaping embedded within a SAR ADC has been utilized to suppress these noise sources with minimal overhead [1]–[2]. The maximum reported conversion rate of 10 to 12b 1b/step SAR ADCs is $sim 400$ MS/s, and hence the available bandwidth is limited to 50MHz given an OSR of 4-6. The NS pipeline-SAR ADC [3] was introduced to overcome this limitation by virtue of its superior speed, but at the cost of an active amplifier and calibration. To enlarge the bandwidth and increase the SNR of a SAR ADC, a timeinterleaved noise-shaping SAR (TINS-SAR) architecture is a promising solution [4]. This work presents a passive TI noise-shaping technique to enable a power-efficient, PVT-robust ADC for 80MHz BW and 70dB DR.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115004222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365762
Jong-Seok Park, Sushil Subramanian, L. Lampert, T. Mladenov, Ilya V. Klotchkov, Dileep Kurian, E. Juárez-Hernández, Brando Perez Esparza, S. Kale, K. T. A. Beevi, S. Premaratne, T. Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, S. Pellerano
Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a $mu$-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.
{"title":"A Fully Integrated Cryo-CMOS SoC for Qubit Control in Quantum Computers Capable of State Manipulation, Readout and High-Speed Gate Pulsing of Spin Qubits in Intel 22nm FFL FinFET Technology","authors":"Jong-Seok Park, Sushil Subramanian, L. Lampert, T. Mladenov, Ilya V. Klotchkov, Dileep Kurian, E. Juárez-Hernández, Brando Perez Esparza, S. Kale, K. T. A. Beevi, S. Premaratne, T. Watson, Satoshi Suzuki, Mustafijur Rahman, Jaykant Timbadiya, Saksham Soni, S. Pellerano","doi":"10.1109/ISSCC42613.2021.9365762","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365762","url":null,"abstract":"Quantum computing promises exponential speed-up in solving certain complex problems that would be intractable by classical computers. However, thousands or millions of qubits might be required to solve useful problems. High-precision and low-noise electrical signals are required to manipulate and read the state of a qubit and to control qubit-to-qubit interactions. Current systems use room temperature electronics with many coax cables routed to the qubit chip inside a dilution refrigerator. This approach does not scale to large number of qubits, due to form factor, cost, power consumption and thermal load to the fridge. To address this challenge, a cryogenic qubit controller has been proposed [1]. The first integrated implementation of a cryogenic pulse modulator has been presented in [2], demonstrating the capability of manipulating (drive) the state of superconducting qubits. The work in [3] extends the capability of the controller with 3 main features: frequency-multiplexing to reduce the number of RF cables per qubit, an arbitrary I/Q pulse generation for improved control fidelity and a digitally-intensive architecture with integrated instruction set to enable integration in existing quantum control stacks. This work further advances the prior art by integrating the capability of reading the qubit state and generating the voltage pulses required for drive, readout, 2-qubit operations and qubit characterization. The SoC can drive up to 16 spin qubits by frequency multiplexing over a single RF line, read the state of up to 6 qubits simultaneously and control up to 22 gate potentials. The SoC also integrates a $mu$-controller for increased flexibility in implementing the control instruction set. The proposed cryogenic controller can replace all the high-speed control electronics used in conventional solutions today, paving the way towards scalable quantum computers.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"123 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115413992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage $left(V_{mathrm{dd}}right)$ domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1–5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive $V_{ {dd }}$ margining. Operation at an elevated $V_{ {dd }}$ -and, therefore, the load-current $left(I_{ {load }}right)$ - inflates power draw and further reduces system efficiency $left(eta_{ {system }}right)$, i.e. the ratio of the useful (margin-free) output power to input power draw.
{"title":"A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS","authors":"Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, V. Sathe","doi":"10.1109/ISSCC42613.2021.9365760","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365760","url":null,"abstract":"Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage $left(V_{mathrm{dd}}right)$ domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1–5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive $V_{ {dd }}$ margining. Operation at an elevated $V_{ {dd }}$ -and, therefore, the load-current $left(I_{ {load }}right)$ - inflates power draw and further reduces system efficiency $left(eta_{ {system }}right)$, i.e. the ratio of the useful (margin-free) output power to input power draw.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115723119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365849
M. Montazerolghaem, S. Pires, L. D. Vreede, M. Babaie
The introduction of the fifth-generation (5G) New Radio (NR) standard has imposed several challenges in the design of sub-6GHz receivers (RX). Firstly, the maximum channel bandwidth(2BW) increases to 100MHz, while a -15dBm continuous-wave (CW) blocker can be located only $Delta$ f=85MHz away from the desired band edge. Such a small $Delta$ f/BW($sim$2) places a stringent linearity requirement on an RX, thus demanding the use of higher-order filtering. Secondly, in-band (IB) linearity also becomes critical, since the band of interest may contain many signals resulting from carrier aggregation and digital beamforming 0peration. Finally, a sub-3dB noise Figure (NF) is required to achieve the highest possible link budget, which allows to maximize the spectral efficiency and data rate.
{"title":"6.5 A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications","authors":"M. Montazerolghaem, S. Pires, L. D. Vreede, M. Babaie","doi":"10.1109/ISSCC42613.2021.9365849","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365849","url":null,"abstract":"The introduction of the fifth-generation (5G) New Radio (NR) standard has imposed several challenges in the design of sub-6GHz receivers (RX). Firstly, the maximum channel bandwidth(2BW) increases to 100MHz, while a -15dBm continuous-wave (CW) blocker can be located only $Delta$ f=85MHz away from the desired band edge. Such a small $Delta$ f/BW($sim$2) places a stringent linearity requirement on an RX, thus demanding the use of higher-order filtering. Secondly, in-band (IB) linearity also becomes critical, since the band of interest may contain many signals resulting from carrier aggregation and digital beamforming 0peration. Finally, a sub-3dB noise Figure (NF) is required to achieve the highest possible link budget, which allows to maximize the spectral efficiency and data rate.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116647775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365759
S. Naghavi, Saghar Seyedabbaszadehesfahlani, F. Khoeini, A. Cathelin, E. Afshari
The increasing demands for compact, low-cost, and high-resolution radar systems have pushed the operation frequency to the terahertz range due to the shorter wavelength and larger available bandwidth [1–5]. However, the best-reported range resolution cannot go below 1.5mm with a 100GHz bandwidth [1], which is not enough for many industrial applications like small-defect detection and surface screening. Moreover, most previous works [3–5] are based on conventional transceiver architectures that use separate antennas for TX and RX or use parallel multi-antenna designs to increase the frequency bandwidth [1]. These structures not only increase the chip size but also degrade the radar performance when they are placed at the focal point of a collimating lens. This degradation occurs due to the separated antenna phase centers, which are not well located at the collimating lens focal point, causing a multi-beam radiation pattern. To overcome these challenges, we have adopted an autodyne FMCW radar structure [6, 7] with a phase processing method on the radar IF signal [7]. The autodyne is an oscillator that simultaneously carries out functions of generating the transmission and mixing the transmitted and reflected signals. There is no separate path for the RX signal in the autodyne, as the radiated and reflected signals exist at the same point of the autodyne circuit. Hence, it utilizes a combined antenna with a single-phase center for both transmitting and receiving parts. Besides, the phase processing method allows us to measure short ranges with an error no more than one-tenth of one-percent, which in terahertz frequencies provides micrometer resolutions [7]. Using these approaches, this paper demonstrates an autodyne FMCW radar with 66.7GHz bandwidth from 191GHz to 257.7GHz with a minimum range resolution of $54 mu mathrm{m}$. Across state-of-the-art, this design improves the range resolution by 28 times.
由于更短的波长和更大的可用带宽，对紧凑、低成本和高分辨率雷达系统日益增长的需求将工作频率推向了太赫兹范围[1-5]。然而，在100GHz带宽下，报道的最佳距离分辨率不能低于1.5mm[1]，这对于小缺陷检测和表面筛选等许多工业应用来说是不够的。此外，大多数先前的工作[3-5]都是基于传统的收发器架构，即对TX和RX使用单独的天线或使用并行多天线设计来增加频率带宽[1]。这些结构不仅增加了芯片的尺寸，而且当它们被放置在准直透镜的焦点时，会降低雷达的性能。这种退化是由于分离的天线相位中心没有很好地定位在准直透镜的焦点上，导致多波束辐射方向图。为了克服这些挑战，我们采用了一种对雷达中频信号进行相位处理的自达因FMCW雷达结构[6,7]。自激器是一种振荡器，它同时执行产生发射信号和混合发射和反射信号的功能。由于辐射信号和反射信号存在于自达因电路的同一点，因此RX信号在自达因中没有单独的路径。因此，它利用具有单相中心的组合天线用于发射和接收部分。此外，相位处理方法允许我们测量短距离，误差不超过百分之一的十分之一，这在太赫兹频率下提供微米分辨率[7]。利用这些方法，本文演示了一种66.7GHz带宽为191GHz至257.7GHz的自达因FMCW雷达，其最小距离分辨率为$54 mu mathm {m}$。通过最先进的技术，这种设计将距离分辨率提高了28倍。
{"title":"A 250GHz Autodyne FMCW Radar in 55nm BiCMOS with Micrometer Range Resolution","authors":"S. Naghavi, Saghar Seyedabbaszadehesfahlani, F. Khoeini, A. Cathelin, E. Afshari","doi":"10.1109/ISSCC42613.2021.9365759","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365759","url":null,"abstract":"The increasing demands for compact, low-cost, and high-resolution radar systems have pushed the operation frequency to the terahertz range due to the shorter wavelength and larger available bandwidth [1–5]. However, the best-reported range resolution cannot go below 1.5mm with a 100GHz bandwidth [1], which is not enough for many industrial applications like small-defect detection and surface screening. Moreover, most previous works [3–5] are based on conventional transceiver architectures that use separate antennas for TX and RX or use parallel multi-antenna designs to increase the frequency bandwidth [1]. These structures not only increase the chip size but also degrade the radar performance when they are placed at the focal point of a collimating lens. This degradation occurs due to the separated antenna phase centers, which are not well located at the collimating lens focal point, causing a multi-beam radiation pattern. To overcome these challenges, we have adopted an autodyne FMCW radar structure [6, 7] with a phase processing method on the radar IF signal [7]. The autodyne is an oscillator that simultaneously carries out functions of generating the transmission and mixing the transmitted and reflected signals. There is no separate path for the RX signal in the autodyne, as the radiated and reflected signals exist at the same point of the autodyne circuit. Hence, it utilizes a combined antenna with a single-phase center for both transmitting and receiving parts. Besides, the phase processing method allows us to measure short ranges with an error no more than one-tenth of one-percent, which in terahertz frequencies provides micrometer resolutions [7]. Using these approaches, this paper demonstrates an autodyne FMCW radar with 66.7GHz bandwidth from 191GHz to 257.7GHz with a minimum range resolution of $54 mu mathrm{m}$. Across state-of-the-art, this design improves the range resolution by 28 times.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116920248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365969
Dewei Wang, S. Kim, Minhao Yang, A. Lazar, Mingoo Seok
In mobile and edge devices, always-on keyword spotting (KWS) is an essential function to detect wake-up words. Recent works achieved extremely low power dissipation down to $sim500$ nW [1]. However, most of them adopt noise-dependent training, i.e. training for a specific signal-to-noise ratio (SNR) and noise type [1], and therefore their accuracies degrade for different SNR levels and noise types that are not targeted in the training (Fig. 9.9.1, top left). To improve robustness, so-called noise-independent training can be considered, which is to use the training data that includes all the possible SNR levels and noise types [2]. But, this approach is challenging for an ultra-low-power device since it demands a large neural network to learn all the possible features. A neural network of a fixed size has its own memory capacity limit and reaches a plateau in accuracy if it has to learn more than its limit (Fig. 9.9.1, top right). On the other hand, it is known that biological acoustic systems employ a simpler process, called divisive energy normalization (DN), to maintain accuracy even in varying noise conditions [3]. In this work, therefore, by adopting such a DN, we prototype a normalized acoustic feature extractor chip (NAFE) in 65nm. The NAFE can take an acoustic signal from a microphone and produce spike-rate coded features. We pair NAFE with a spiking neural network (SNN) classifier chip [4], creating the end-to-end KWS system. The proposed system achieves 89-to-94% accuracy across -5 to 20dB SNRs and four different noise types on HeySnips [5], while the baseline without DN achieves a much lower accuracy of 71-87%. NAFE consumes up to 109nW and the KWS system 570nW.
{"title":"A Background-Noise and Process-Variation-Tolerant 109nW Acoustic Feature Extractor Based on Spike-Domain Divisive-Energy Normalization for an Always-On Keyword Spotting Device","authors":"Dewei Wang, S. Kim, Minhao Yang, A. Lazar, Mingoo Seok","doi":"10.1109/ISSCC42613.2021.9365969","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365969","url":null,"abstract":"In mobile and edge devices, always-on keyword spotting (KWS) is an essential function to detect wake-up words. Recent works achieved extremely low power dissipation down to $sim500$ nW [1]. However, most of them adopt noise-dependent training, i.e. training for a specific signal-to-noise ratio (SNR) and noise type [1], and therefore their accuracies degrade for different SNR levels and noise types that are not targeted in the training (Fig. 9.9.1, top left). To improve robustness, so-called noise-independent training can be considered, which is to use the training data that includes all the possible SNR levels and noise types [2]. But, this approach is challenging for an ultra-low-power device since it demands a large neural network to learn all the possible features. A neural network of a fixed size has its own memory capacity limit and reaches a plateau in accuracy if it has to learn more than its limit (Fig. 9.9.1, top right). On the other hand, it is known that biological acoustic systems employ a simpler process, called divisive energy normalization (DN), to maintain accuracy even in varying noise conditions [3]. In this work, therefore, by adopting such a DN, we prototype a normalized acoustic feature extractor chip (NAFE) in 65nm. The NAFE can take an acoustic signal from a microphone and produce spike-rate coded features. We pair NAFE with a spiking neural network (SNN) classifier chip [4], creating the end-to-end KWS system. The proposed system achieves 89-to-94% accuracy across -5 to 20dB SNRs and four different noise types on HeySnips [5], while the baseline without DN achieves a much lower accuracy of 71-87%. NAFE consumes up to 109nW and the KWS system 570nW.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"38 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120923239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/isscc42613.2021.9365934
{"title":"ISSCC 2021 Table of Contents","authors":"","doi":"10.1109/isscc42613.2021.9365934","DOIUrl":"https://doi.org/10.1109/isscc42613.2021.9365934","url":null,"abstract":"","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129550824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366044
Geunhaeng Lee, Sanghwa Lee, Ji-Hoon Kim, Tae Wook Kim
As the amount of information that wireless communication devices carry increases more than ever, the importance of data transmission speed and efficiency has drastically increased. Thus, the need has emerged for high-data-rate, low-power communication. Impulse-radio ultra-wideband (IR-UWB) technology is considered a suitable candidate for such needs. The latest studies have introduced various techniques to increase data rate as well as communication range while reducing power consumption, notably analog frequency hopping (AFH), which increases communication distance by increasing pulse energy [1], multiband IR-UWB communication that utilizes high-order modulation techniques to obtain the Gb/s data rate [2]–[3], and digitalized multi-pulse-position modulation (D-MPPM) [4] to mitigate the dependence of the data rate on the symbol period for low-power high-speed communication. However there is still room to achieve lower power, while maintaining Gb/s speeds, and proper radio-range communication. This work proposes several techniques to achieve Gb/s data rates while maintaining tens of mW of power consumption and a few meters of communication range. Firstly extended multi-pulse-position modulation (E-MPPM) is proposed to increase data rate, secondly a high-conversion-gain cross-coupled envelope detector is proposed for improving the sensitivity and finally, a new digital frequency-hopping (DFH) technique is proposed to increase radio range by increasing pulse energy.
{"title":"21.1 A 1.125Gb/s 28mW 2m-Radio-Range IR-UWB CMOS Transceiver","authors":"Geunhaeng Lee, Sanghwa Lee, Ji-Hoon Kim, Tae Wook Kim","doi":"10.1109/ISSCC42613.2021.9366044","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366044","url":null,"abstract":"As the amount of information that wireless communication devices carry increases more than ever, the importance of data transmission speed and efficiency has drastically increased. Thus, the need has emerged for high-data-rate, low-power communication. Impulse-radio ultra-wideband (IR-UWB) technology is considered a suitable candidate for such needs. The latest studies have introduced various techniques to increase data rate as well as communication range while reducing power consumption, notably analog frequency hopping (AFH), which increases communication distance by increasing pulse energy [1], multiband IR-UWB communication that utilizes high-order modulation techniques to obtain the Gb/s data rate [2]–[3], and digitalized multi-pulse-position modulation (D-MPPM) [4] to mitigate the dependence of the data rate on the symbol period for low-power high-speed communication. However there is still room to achieve lower power, while maintaining Gb/s speeds, and proper radio-range communication. This work proposes several techniques to achieve Gb/s data rates while maintaining tens of mW of power consumption and a few meters of communication range. Firstly extended multi-pulse-position modulation (E-MPPM) is proposed to increase data rate, secondly a high-conversion-gain cross-coupled envelope detector is proposed for improving the sensitivity and finally, a new digital frequency-hopping (DFH) technique is proposed to increase radio range by increasing pulse energy.","PeriodicalId":371093,"journal":{"name":"2021 IEEE International Solid- State Circuits Conference (ISSCC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124610904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365848
Bagas Prabowo, G. Zheng, M. Mehrpoo, B. Patra, P. Harvey-Collard, Jurgen Dijkema, A. Sammak, Giordano Scappucci, E. Charbon, F. Sebastiano, L. Vandersypen, M. Babaie
Quantum computers (QC) promise to solve certain computational problems exponentially faster than a classical computer due to the superposition and entanglement properties of quantum bits (qubits). Among several qubit technologies, spin qubits are a promising candidate for large-scale QC, since (1) they have a small footprint allowing them to be densely integrated and (2) they can operate at relatively high temperatures $(gt1mathrm{K})$ [1], potentially reducing system cost and complexity.
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