Hardware neuron models with CMOS for auditory neural networks

K. Saeki, R. Iidaka, Y. Sekine, K. Aihara
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引用次数: 3

Abstract

A number of studies have recently been made on hardware implementation of a neuron model for applications to information processing functions of neural networks. We previously proposed the transfer function which changes the threshold of a pulse-type hardware neuron model (hereafter, "P-HNM") in time according to an output that express feature-detecting cell and a universal-type hardware neuron model using depletion mode MOSFETs (hereafter "D-MOSFETs"), resistors, and capacitors. However, because it is difficult to make D-MOSFETs due to a complicated manufacturing process, they are not usually used in IC implementation. In this paper, we propose hardware neuron models with CMOS for feature-detecting cells of auditory neural network.
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听觉神经网络的CMOS硬件神经元模型
近年来,人们对神经元模型的硬件实现进行了大量的研究,以应用于神经网络的信息处理功能。我们之前提出了传递函数,该传递函数根据表示特征检测细胞的输出及时改变脉冲型硬件神经元模型(以下简称“P-HNM”)的阈值,以及使用耗尽模式mosfet(以下简称“d - mosfet”),电阻和电容器的通用型硬件神经元模型。然而,由于制造工艺复杂,d - mosfet难以制造,因此通常不用于IC实现。本文提出了基于CMOS的听觉神经网络特征检测单元的硬件神经元模型。
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