A 40 nm LP CMOS self-biased continuous-time comparator with sub-100ps delay at 1.1V & 1.2mW

Abstract

A fully differential continuous-time comparator, that consists of a preamplifier-latch cascade, achieves propagation delays of 99 ps for a 50mVpp and 74 ps for a 100mVpp input signal amplitude under 1.1V supply and 1.2mW power consumption. The comparator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. Dynamic delay-power management is supported through digital programmability of the self-biasing and supply voltage scaling. The design occupies 0.0007mm2 in 40 nm LP CMOS process.