Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649065
Zhipeng Li, Yan Li, Y. Avniel, A. Megretski, V. Stojanović
Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ~2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing and 22pJ/sample for linear amplification with nonlinear components, at throughput of 400MSample/s and areas of 0.2-0.4mm2 in 45nm SOI process.
{"title":"Design trade-offs in signal component separators for outphasing power amplifiers","authors":"Zhipeng Li, Yan Li, Y. Avniel, A. Megretski, V. Stojanović","doi":"10.1109/ESSCIRC.2013.6649065","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649065","url":null,"abstract":"Implementation design space of piece-wise linear outphasing signal component separator is explored by utilizing the changes in micro-architecture, choice of storage elements and aggressive back-end leakage power optimization techniques. With combination of these techniques, ~2× energy and area savings are achieved, resulting in record energy-efficiency of 32pJ/sample for asymmetric multilevel outphasing and 22pJ/sample for linear amplification with nonlinear components, at throughput of 400MSample/s and areas of 0.2-0.4mm2 in 45nm SOI process.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115299493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649136
Keishi Tsubaki, T. Hirose, N. Kuroki, M. Numa
This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively.
{"title":"A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application","authors":"Keishi Tsubaki, T. Hirose, N. Kuroki, M. Numa","doi":"10.1109/ESSCIRC.2013.6649136","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649136","url":null,"abstract":"This paper proposes an ultra-low power fully on-chip CMOS relaxation oscillator (ROSC) for a real-time clock application. The circuit has a distinctive feature in compensation architecture of a comparator's non-idealities caused by offset voltage and delay time. The ROSC can generate a stable and higher oscillation clock frequency without increasing power by using a low reference voltage and employing a novel compensation architecture for comparators. Measurement results in a 0.18-μm CMOS process demonstrated that the circuit can generate a stable clock frequency of 32.55 kHz. The power dissipation was 472 nW. Measured line regulation and temperature coefficient were 1.1%/V and 120ppm/°C, respectively.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117234854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649068
Y. Niki, D. Miyashita, Hiroyuki Kobayashi, S. Kousai
We propose a supply noise rejection technique, which is applied to an all-digital phase-locked loop (ADPLL). Supply noise is cancelled by adding a cancellation current whose fluctuation is the same as that of a supply-noise component in an oscillator current. The proposed technique is realized with a small area and current dissipation, and is tolerant to process, voltage, and temperature (PVT) variations without calibration. The proof-of-concept chip was fabricated using a 65 nm CMOS technology. It was measured that the peak-to-peak jitter was reduced by 54 % in the presence of 30 mVpp, 15 MHz supply noise, and the robustness of the proposed technique was verified by the measurements.
{"title":"A supply-noise-rejection technique in ADPLL with noise-cancelling current source","authors":"Y. Niki, D. Miyashita, Hiroyuki Kobayashi, S. Kousai","doi":"10.1109/ESSCIRC.2013.6649068","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649068","url":null,"abstract":"We propose a supply noise rejection technique, which is applied to an all-digital phase-locked loop (ADPLL). Supply noise is cancelled by adding a cancellation current whose fluctuation is the same as that of a supply-noise component in an oscillator current. The proposed technique is realized with a small area and current dissipation, and is tolerant to process, voltage, and temperature (PVT) variations without calibration. The proof-of-concept chip was fabricated using a 65 nm CMOS technology. It was measured that the peak-to-peak jitter was reduced by 54 % in the presence of 30 mVpp, 15 MHz supply noise, and the robustness of the proposed technique was verified by the measurements.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127460568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649063
B. Murmann
Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital resources to enhance performance-limiting analog building blocks has become a widely explored paradigm in modern ICs. This paper reviews the state-of-the-art in digitally assisted data converter design and provides an overview of commonly used techniques.
{"title":"Digitally assisted data converter design","authors":"B. Murmann","doi":"10.1109/ESSCIRC.2013.6649063","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649063","url":null,"abstract":"Modern CMOS technologies provide digital signal processing capabilities at high integration density and low energy per operation. Hence, expending digital resources to enhance performance-limiting analog building blocks has become a widely explored paradigm in modern ICs. This paper reviews the state-of-the-art in digitally assisted data converter design and provides an overview of commonly used techniques.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649076
Samuel Foulon, S. Pruvost, D. Pache, C. Loyez, N. Rolland
A 142GHz fully-integrated wireless chip-to-chip solution is demonstrated for short range and low power communication. Implemented in 0.13μm SiGe:C BiCMOS technology, the Tx and Rx silicon area including dipole antennas is 0.31mm2. The OOK transceiver achieves a data rate of 14Gbps for a communication distance of 0.6mm with an energy efficiency of 5.7pJ/bit.
{"title":"A 142GHz fully integrated wireless chip to chip communication system for high data rate operation","authors":"Samuel Foulon, S. Pruvost, D. Pache, C. Loyez, N. Rolland","doi":"10.1109/ESSCIRC.2013.6649076","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649076","url":null,"abstract":"A 142GHz fully-integrated wireless chip-to-chip solution is demonstrated for short range and low power communication. Implemented in 0.13μm SiGe:C BiCMOS technology, the Tx and Rx silicon area including dipole antennas is 0.31mm2. The OOK transceiver achieves a data rate of 14Gbps for a communication distance of 0.6mm with an energy efficiency of 5.7pJ/bit.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126976800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649134
V. D. Smedt, G. Gielen, W. Dehaene
A low-power, fully-integrated 40nm-CMOS timing and receiver circuit for wireless sensor networks is presented. The timing circuit locks on a 30 MHz injected signal which is amplitude modulated on a 2.4 GHz wirelessly received carrier. Phase shifts in the injected signal can be detected, which facilitates the possibility to use the circuit as a low-data-rate network coordination receiver. The oscillator circuit is able to lock to a -66 dBm RF signal with a 30 % modulation depth over a +/- 22 % lock range. The receiver data-rate is around 1.8 Mbit/s. The circuit can deliver a stable clock reference over a 0.7 to 1.5 V supply voltage range and a -20 to 100°C temperature range. The total power consumption of the clock reference and the receiver is 72 μW which makes it suitable for ultra-low-power applications such as RF-powered wireless sensor nodes. The injection-locked clock reference as well as the coordination receiver result in a large power savings compared to other, more inaccurate, timing and receiver solutions.
{"title":"A 40nm-CMOS, 72 µW injection-locked timing reference and 1.8 Mbit/s coordination receiver for wireless sensor networks","authors":"V. D. Smedt, G. Gielen, W. Dehaene","doi":"10.1109/ESSCIRC.2013.6649134","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649134","url":null,"abstract":"A low-power, fully-integrated 40nm-CMOS timing and receiver circuit for wireless sensor networks is presented. The timing circuit locks on a 30 MHz injected signal which is amplitude modulated on a 2.4 GHz wirelessly received carrier. Phase shifts in the injected signal can be detected, which facilitates the possibility to use the circuit as a low-data-rate network coordination receiver. The oscillator circuit is able to lock to a -66 dBm RF signal with a 30 % modulation depth over a +/- 22 % lock range. The receiver data-rate is around 1.8 Mbit/s. The circuit can deliver a stable clock reference over a 0.7 to 1.5 V supply voltage range and a -20 to 100°C temperature range. The total power consumption of the clock reference and the receiver is 72 μW which makes it suitable for ultra-low-power applications such as RF-powered wireless sensor nodes. The injection-locked clock reference as well as the coordination receiver result in a large power savings compared to other, more inaccurate, timing and receiver solutions.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123641426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649163
R. Ganesan, J. Krumm, S. Pankalla, Klaus Ludwig, M. Glesner
We demonstrate an organic smart label electronic system using p-type organic thin film transistors (OTFT) for temperature sensing applications. The electronic label consists of all organic temperature sensor, memory, logic and interface circuits and detects whether the critical temperature threshold value has been exceeded and records the data digitally in write-once-read-many (WORM) form that can be transmitted to a reader through wireless communication. A comparator is used to interface the sensor to the logic part. The logic circuit block processes and bundles the sensor information along with the necessary additional information that is required for a successful wireless transmission. We have demonstrated the operation of the reported organic smart label system using a silicon based modulator/rectifier circuit for RF communication. The organic logic circuit was built using standard cell design approach with approximately 180 p-type OTFTs. All the circuits were operated with a VDD of -20 V.
{"title":"Design of an organic electronic label on a flexible substrate for temperature sensing","authors":"R. Ganesan, J. Krumm, S. Pankalla, Klaus Ludwig, M. Glesner","doi":"10.1109/ESSCIRC.2013.6649163","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649163","url":null,"abstract":"We demonstrate an organic smart label electronic system using p-type organic thin film transistors (OTFT) for temperature sensing applications. The electronic label consists of all organic temperature sensor, memory, logic and interface circuits and detects whether the critical temperature threshold value has been exceeded and records the data digitally in write-once-read-many (WORM) form that can be transmitted to a reader through wireless communication. A comparator is used to interface the sensor to the logic part. The logic circuit block processes and bundles the sensor information along with the necessary additional information that is required for a successful wireless transmission. We have demonstrated the operation of the reported organic smart label system using a silicon based modulator/rectifier circuit for RF communication. The organic logic circuit was built using standard cell design approach with approximately 180 p-type OTFTs. All the circuits were operated with a VDD of -20 V.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121292223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649105
Mihail Jefremow, T. Kern, Ulrich Backhausen, J. Elbs, B. Rousseau, Christoph Roll, L. Castro, T. Roehr, E. Paparisto, K. Herfurth, R. Bartenschlager, Stefanie Thierold, R. Renardy, Stephan Kassenetter, N. Lawal, M. Strasser, W. Trottmann, D. Schmitt-Landsiedel
This paper presents a 65nm embedded flash macro for automotive applications with read and write throughput of 5.7GB/s and 1.4MB/s respectively. The high read throughput rate is achieved by using the multi voltage domain multiplexer design enabling a low voltage read path and the local ground referenced read circuit design utilizing the robust time domain source side sense amplifier (SoSiSA) [1]. This allows low voltage sub 50mV swing read operation for high speed read-out under more than 30mV system noise. The hot source triple poly (HS3P) embedded flash memory cell [2] allows sub 5μs low current write operation enabling high write throughput up to a junction temperature of 170°C.
{"title":"A 65nm 4MB embedded flash macro for automotive achieving a read throughput of 5.7GB/s and a write throughput of 1.4MB/s","authors":"Mihail Jefremow, T. Kern, Ulrich Backhausen, J. Elbs, B. Rousseau, Christoph Roll, L. Castro, T. Roehr, E. Paparisto, K. Herfurth, R. Bartenschlager, Stefanie Thierold, R. Renardy, Stephan Kassenetter, N. Lawal, M. Strasser, W. Trottmann, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIRC.2013.6649105","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649105","url":null,"abstract":"This paper presents a 65nm embedded flash macro for automotive applications with read and write throughput of 5.7GB/s and 1.4MB/s respectively. The high read throughput rate is achieved by using the multi voltage domain multiplexer design enabling a low voltage read path and the local ground referenced read circuit design utilizing the robust time domain source side sense amplifier (SoSiSA) [1]. This allows low voltage sub 50mV swing read operation for high speed read-out under more than 30mV system noise. The hot source triple poly (HS3P) embedded flash memory cell [2] allows sub 5μs low current write operation enabling high write throughput up to a junction temperature of 170°C.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116185383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649126
Charles Wu, B. Nikolić
A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A multi-level (two-bit) non-return-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier guarantees a highly linear front end. The peak SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of +10 dBm and an IIP2 of +50 dBm is achieved while dissipating only 40 mW from 1.1 V / 1.5 V supply voltages.
{"title":"A 0.4 GHz – 4 GHz direct RF-to-digital ΣΔ multi-mode receiver","authors":"Charles Wu, B. Nikolić","doi":"10.1109/ESSCIRC.2013.6649126","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649126","url":null,"abstract":"A wide-tuning-range low-power sigma-delta-based direct-RF-to-digital receiver architecture is implemented in 65 nm CMOS. A multi-level (two-bit) non-return-to-zero DAC improves jitter immunity to enable a high dynamic range, and, with a class-AB low-noise transconductance amplifier guarantees a highly linear front end. The peak SNDR of the receiver exceeds 68 dB for a 4 MHz signal, and is better than 60 dB across the 400 MHz to 4 GHz carrier frequency range. By virtue of utilizing a negative feedback digitizer close to the antenna, an IIP3 of +10 dBm and an IIP2 of +50 dBm is achieved while dissipating only 40 mW from 1.1 V / 1.5 V supply voltages.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130405812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-31DOI: 10.1109/ESSCIRC.2013.6649079
Haifeng Ma, R. V. D. Zee, B. Nauta
In this paper we present a highly-efficient 80V class-D power stage design in a 0.14μm SOI-based BCD process. Immunity to the on-chip supply bounce is realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and minimized switching loss are achieved with a 94% peak efficiency in the realized chip.
{"title":"An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process","authors":"Haifeng Ma, R. V. D. Zee, B. Nauta","doi":"10.1109/ESSCIRC.2013.6649079","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649079","url":null,"abstract":"In this paper we present a highly-efficient 80V class-D power stage design in a 0.14μm SOI-based BCD process. Immunity to the on-chip supply bounce is realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transition and minimized switching loss are achieved with a 94% peak efficiency in the realized chip.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124158493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：