Design of Evaluation Board for Image Processing ASIC and VHDL Implementation of FPGA Interface

Abstract

The growing usage of reconfigurable Field Programmable Gate Arrays (FPGAs) and increased number of Application Specific Integrated Circuits (ASICs) designed for different applications have uplifted the technology to certain level compared to previous decades. The paper aims at building a FPGA based evaluation board to verify the functionality of the image processing ASIC. It provides complete information about building the evaluation board, different aspects in VHDL implementation and coding strategies to configure the FPGA. The code is executed in XILINX 14.5 design suite and simulated using Questa sim 6.3c simulator. Simulation results are presented at the end and are functionally checked. The different components and ICs used are precisely explained. This paper thus provides an efficient and fast ASIC verification process on a FPGA based platform. The board is cost effective since the FPGA is cheap and is easily available and the re-configurability of the FPGA makes the project more effective.