The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408) Pub Date : 2003-06-12 DOI:10.1109/VLSIC.2003.1221226

T. Ohkawa, T. Nozawa, M. Fujibayashi, N. Miyamoto, K. Leo, S. Kita, K. Kotani, T. Ohmi

引用次数: 5

Abstract

A dynamically reconfigurable logic array, i.e., the Flexible Processor, suitable for single chip emulation system is developed. It demonstrates the sequential execution of sub-circuits divided from original circuit, by newly developed Temporal Communication Module (TCM). In order to accelerate emulation speed, a logic element, which can reduce configuration data by 30% as compared to conventional Look-Up-Table, is implemented. The chip (3.9/spl times/3.9 mm/sup 2/) fabricated with 0.6 /spl mu/m CMOS technology operates at 33 MHz with 5.0 V power supply.

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柔性处理器——用于个人使用仿真系统的动态可重构逻辑阵列

开发了一种适用于单片机仿真系统的动态可重构逻辑阵列，即柔性处理器。通过新开发的时序通信模块(TCM)，演示了从原始电路中划分出的子电路的顺序执行。为了加快仿真速度，实现了一个逻辑元件，与传统的查找表相比，它可以减少30%的配置数据。采用0.6 /spl mu/m CMOS技术制造的芯片(3.9/spl times/3.9 mm/sup 2/)在5.0 V电源下工作在33 MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

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