Pub Date : 2004-06-01DOI: 10.1109/JSSC.2004.825247
A. Abidi
All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads on a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF CMOS evolve in the future? This paper offers a retrospective and a perspective.
{"title":"RF CMOS comes of age","authors":"A. Abidi","doi":"10.1109/JSSC.2004.825247","DOIUrl":"https://doi.org/10.1109/JSSC.2004.825247","url":null,"abstract":"All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads on a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF CMOS evolve in the future? This paper offers a retrospective and a perspective.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130706522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-30DOI: 10.1109/JSSC.2004.825119
Jri Lee, Behzad Razavi
A frequency divider employs resonance techniques by means of on-chip spiral inductors to operate at high speeds. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.
{"title":"A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology","authors":"Jri Lee, Behzad Razavi","doi":"10.1109/JSSC.2004.825119","DOIUrl":"https://doi.org/10.1109/JSSC.2004.825119","url":null,"abstract":"A frequency divider employs resonance techniques by means of on-chip spiral inductors to operate at high speeds. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125076060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-30DOI: 10.1109/JSSC.2004.825120
A. Muhtaroğlu, G. Taylor, T. Rahal-Arabi
Understanding the supply fluctuations of various frequency harmonics is essential to maximizing microprocessor performance. Conventional methods used for analog validation of the power delivery system fall short in one or more of: a) Measurement accuracy in both frequency and time domains, especially for very high frequency noise caused by large di/dt events. The multi-GHz power supply noise attenuates very quickly away from the die. Conventional approaches of measuring the noise at the pins of the package or at the die using capacitive probes are not accurate for multi-GHz clocks. For this reason, the observability of high frequency on die noise has been very tricky. b) Implementation, e.g. delivery of analog references to multiple areas across a "noisy" die, and compactness/modularity of the measurement units. c) Automation to enable a timely volume of measurements. The efficiency of the measurements is key to correlating a particular speed path to poser supply noise. To address the above issues this paper presents an On-Die Droop Detector (ODDD), a scaleable IC solution implemented and validated on a 90 nm process, for analog sensing of differential high bandwidth supply noise.
{"title":"On-die droop detector for analog sensing of power supply noise","authors":"A. Muhtaroğlu, G. Taylor, T. Rahal-Arabi","doi":"10.1109/JSSC.2004.825120","DOIUrl":"https://doi.org/10.1109/JSSC.2004.825120","url":null,"abstract":"Understanding the supply fluctuations of various frequency harmonics is essential to maximizing microprocessor performance. Conventional methods used for analog validation of the power delivery system fall short in one or more of: a) Measurement accuracy in both frequency and time domains, especially for very high frequency noise caused by large di/dt events. The multi-GHz power supply noise attenuates very quickly away from the die. Conventional approaches of measuring the noise at the pins of the package or at the die using capacitive probes are not accurate for multi-GHz clocks. For this reason, the observability of high frequency on die noise has been very tricky. b) Implementation, e.g. delivery of analog references to multiple areas across a \"noisy\" die, and compactness/modularity of the measurement units. c) Automation to enable a timely volume of measurements. The efficiency of the measurements is key to correlating a particular speed path to poser supply noise. To address the above issues this paper presents an On-Die Droop Detector (ODDD), a scaleable IC solution implemented and validated on a 90 nm process, for analog sensing of differential high bandwidth supply noise.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125306407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-30DOI: 10.1109/JSSC.2004.825233
T. Kadoyama, N. Suzuki, N. Sasho, H. Iizuka, I. Nagase, H. Usukubo, M. Katakura
We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC., in a GPS receiver. The GPS chip, with a total size of 6.4/spl times/6.4 mm, contains a 2.3/spl times/2.0 mm radio part, including RF front end, PLLs, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM and Dual Port SRAM. It's fabricated using 0.18-/spl mu/m CMOS Technology with a MIM option and operates from a 1.6 to 2.0-V power supply. Experimental results show a very low power consumption of, typically, 57-mW for a fully functional chip including baseband, and a high sensitivity of -150 dBm. Through countermeasures for substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external LNA.
为了满足移动GPS应用的小尺寸、低功耗、低成本和高灵敏度等几个重要要求，我们开发了一个完整的单片GPS接收机，采用0.18-/spl μ m CMOS。这是无线电与基带处理器(如SoC)成功结合的第一个案例。，在GPS接收器中。GPS芯片的总尺寸为6.4/spl倍/6.4 mm，包含一个2.3/spl倍/2.0 mm的射频部分，包括射频前端、锁相环、中频功能和500k基带逻辑门，包括掩模ROM、SRAM和双端口SRAM。它采用0.18-/spl mu/m CMOS技术制造，带有MIM选项，工作电源为1.6至2.0 v。实验结果表明，包括基带在内的全功能芯片的功耗非常低，通常为57mw，灵敏度高达- 150dbm。通过对来自数字部分的衬底耦合噪声的对抗，成功地实现了高灵敏度，而不需要任何外部LNA。
{"title":"A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS","authors":"T. Kadoyama, N. Suzuki, N. Sasho, H. Iizuka, I. Nagase, H. Usukubo, M. Katakura","doi":"10.1109/JSSC.2004.825233","DOIUrl":"https://doi.org/10.1109/JSSC.2004.825233","url":null,"abstract":"We have developed a complete single-chip GPS receiver using 0.18-/spl mu/m CMOS to meet several important requirements, such as small size, low power, low cost and high sensitivity for mobile GPS applications. This is the first case in which a radio has been successfully combined with a baseband processor, such as SoC., in a GPS receiver. The GPS chip, with a total size of 6.4/spl times/6.4 mm, contains a 2.3/spl times/2.0 mm radio part, including RF front end, PLLs, IF functions, and 500 K gates of baseband logic, including mask ROM, SRAM and Dual Port SRAM. It's fabricated using 0.18-/spl mu/m CMOS Technology with a MIM option and operates from a 1.6 to 2.0-V power supply. Experimental results show a very low power consumption of, typically, 57-mW for a fully functional chip including baseband, and a high sensitivity of -150 dBm. Through countermeasures for substrate coupling noise from the digital part, the high sensitivity was successfully achieved without any external LNA.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115863134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-30DOI: 10.1109/JSSC.2004.825245
D.B. Barkin, A.C.Y. Lin, D. Su, B. Wooley
An oversampling bandpass cascaded digital-to-analog converter, including digital FIR and analog semi-digital filtering to reduce out of band quantization noise, has been integrated in 0.25-/spl mu/m CMOS technology. The converter has 83 dB of dynamic range for a 6.25-MHz signal band centered at 50-MHz and suppresses out-of-band quantization noise by 40 dB.
一个过采样带通级联数模转换器，包括数字FIR和模拟半数字滤波，以减少带外量化噪声，已集成在0.25-/spl μ m CMOS技术。该转换器在6.25 mhz以50-MHz为中心的信号频带内具有83 dB的动态范围，抑制带外量化噪声40 dB。
{"title":"A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering","authors":"D.B. Barkin, A.C.Y. Lin, D. Su, B. Wooley","doi":"10.1109/JSSC.2004.825245","DOIUrl":"https://doi.org/10.1109/JSSC.2004.825245","url":null,"abstract":"An oversampling bandpass cascaded digital-to-analog converter, including digital FIR and analog semi-digital filtering to reduce out of band quantization noise, has been integrated in 0.25-/spl mu/m CMOS technology. The converter has 83 dB of dynamic range for a 6.25-MHz signal band centered at 50-MHz and suppresses out-of-band quantization noise by 40 dB.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132308349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221225
TingYen Chiang, K. Saraswat
Accurate integrity assessment of on-chip interconnect temperature rise is essential for high performance chip design. This paper presents a compact analytical model for estimating the temperature rise of multilevel ULSI interconnects incorporating via effect. The predicted temperature distributions are shown to be in excellent agreement with the 3-D finite element thermal simulation (ANSYS) results. Additionally, this model provides an efficient approach to analyze realistic chip level interconnect temperature which is extremely difficult to do with ANSYS. Significant difference in temperature distribution and maximum temperature rise is observed between the realistic situation of heat dissipation with vias and the overly simplified case that ignores via effect. The closed-form expression is further applied to evaluate the impact of the interconnect heating on the various design rule parameters and scaling of deep sub-micron Cu/low-k interconnects.
{"title":"Closed-form analytical thermal model for accurate temperature estimation of multilevel ULSI interconnects","authors":"TingYen Chiang, K. Saraswat","doi":"10.1109/VLSIC.2003.1221225","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221225","url":null,"abstract":"Accurate integrity assessment of on-chip interconnect temperature rise is essential for high performance chip design. This paper presents a compact analytical model for estimating the temperature rise of multilevel ULSI interconnects incorporating via effect. The predicted temperature distributions are shown to be in excellent agreement with the 3-D finite element thermal simulation (ANSYS) results. Additionally, this model provides an efficient approach to analyze realistic chip level interconnect temperature which is extremely difficult to do with ANSYS. Significant difference in temperature distribution and maximum temperature rise is observed between the realistic situation of heat dissipation with vias and the overly simplified case that ignores via effect. The closed-form expression is further applied to evaluate the impact of the interconnect heating on the various design rule parameters and scaling of deep sub-micron Cu/low-k interconnects.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115425952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221213
S. Hsu, B. Chatterjee, M. Sachdev, A. Alvandpour, R. Krishnamurthy, S. Borkar
This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.
{"title":"A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme","authors":"S. Hsu, B. Chatterjee, M. Sachdev, A. Alvandpour, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2003.1221213","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221213","url":null,"abstract":"This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125012359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221204
T. Ogura, N. Ogura, M. Kirihara, Ki-Tae Park, Y. Baba, M. Sekine, K. Shimeno
By adding a shared bit diffusion contact to the twin MONOS, a high performance, low voltage, low power NOR-type memory can be achieved. The process is simple and the array maintains its dual density advantage, which makes this flash memory technology suitable for embedded as well as standalone applications. Two fast access embedded designs will be discussed: a) 16 Mb with 15 ns access time and b) 128 Kb with 4 ns access time.
{"title":"Embedded twin MONOS flash memories with 4 ns and 15 ns fast access times","authors":"T. Ogura, N. Ogura, M. Kirihara, Ki-Tae Park, Y. Baba, M. Sekine, K. Shimeno","doi":"10.1109/VLSIC.2003.1221204","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221204","url":null,"abstract":"By adding a shared bit diffusion contact to the twin MONOS, a high performance, low voltage, low power NOR-type memory can be achieved. The process is simple and the array maintains its dual density advantage, which makes this flash memory technology suitable for embedded as well as standalone applications. Two fast access embedded designs will be discussed: a) 16 Mb with 15 ns access time and b) 128 Kb with 4 ns access time.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123597255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221160
T. Saito, H. Yamashita, F. Yuki, T. Baba, A. Koyama, M. Sonehara
We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital "eye-tracking" DR circuit. Fabricated by 0.18-/spl mu/m SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm/sup 2//ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.
{"title":"A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method","authors":"T. Saito, H. Yamashita, F. Yuki, T. Baba, A. Koyama, M. Sonehara","doi":"10.1109/VLSIC.2003.1221160","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221160","url":null,"abstract":"We developed a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Our unique approach of treating a sequential 16-bit incoming data as one unit achieved a fully digital \"eye-tracking\" DR circuit. Fabricated by 0.18-/spl mu/m SiGe-BiCMOS technology, the area of the DR circuit is 0.02-mm/sup 2//ch and its power consumption is 50 mW/ch at 1.8 V. The measured jitter tolerance at 2.5 Gb/s is 0.7 UI p-p, which satisfies the jitter specifications for the SFI-5.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130327341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-06-12DOI: 10.1109/VLSIC.2003.1221168
H. Noda, K. Inoue, H. Mattausch, T. Koide, K. Arimoto
A novel dynamic Ternary-CAM (TCAM) architecture with transparently scheduled refresh, address-input-free writing and planar complementary capacitors is proposed. The planar dynamic concept allows small TCAM cell size of 4.79 /spl mu/m/sup 2/ in a 130 nm CMOS technology that is about half of the static TCAM cell size, and the complementary capacitors improve the stability of conventional-DRAM-based TCAM cells. Transparently scheduled refresh and address-input-free writing make the proposed TCAM especially attractive for classifying applications in network routers.
{"title":"A cost-efficient dynamic Ternary CAM in 130 nm CMOS technology with planar complementary capacitors and TSR architecture","authors":"H. Noda, K. Inoue, H. Mattausch, T. Koide, K. Arimoto","doi":"10.1109/VLSIC.2003.1221168","DOIUrl":"https://doi.org/10.1109/VLSIC.2003.1221168","url":null,"abstract":"A novel dynamic Ternary-CAM (TCAM) architecture with transparently scheduled refresh, address-input-free writing and planar complementary capacitors is proposed. The planar dynamic concept allows small TCAM cell size of 4.79 /spl mu/m/sup 2/ in a 130 nm CMOS technology that is about half of the static TCAM cell size, and the complementary capacitors improve the stability of conventional-DRAM-based TCAM cells. Transparently scheduled refresh and address-input-free writing make the proposed TCAM especially attractive for classifying applications in network routers.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126506668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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