Techniques for embracing intra-cell unbalanced bit error characteristics in MLC NAND flash memory

Abstract

Multi-level per cell (MLC) technique has been widely used to improve the storage density of NAND flash memory. However, bits stored in each MLC memory cell are subject to different bit error rates. In current practice, bits stored in each cell belong to different pages and all the pages are protected using the same ECC tuned for the worst-case scenario, which results in over-protection for other pages and hence reduced storage capacity. In this work, we first develop a flash memory channel model to capture the dominant noise sources such as cell-to-cell interference and random telegraph noise. Using this model, we demonstrate the significant intra-cell unbalanced bit error characteristics for MLC NAND flash memory. We further develop two techniques that can better address this issue to minimize the overall redundancy overhead and hence improve effective capacity. Firstly, we propose an aggregated page programming scheme by modifying the recently emerging full-sequence MLC NAND flash memory programming strategy, which can ensure all the pages experience the same overall bit error rates so that the coding rate of BCH code can be increased by more than 6%. Secondly, in the implementation of non-binary ECC such as RS code, we propose to combine a bit-error-rate-aware symbol grouping scheme in order to further reduce the required coding redundancy.