Energy Efficient Dual Mode DCVSL (DM-DCVSL) design

Abstract

In this work, a modification to existing static DCVSL design is proposed and is referred to as Dual Mode DCVSL(DM-DCVSL) design. The proposed design allows both static and dynamic mode in a single DCVSL structure by including additional transistors. The functionality of the 2-input AND/NAND and XOR/XNOR gates is examined through BSIM4 simulations at PTM 90nm technology node using Symica DE tool. Power, delay and Power Delay Product(PDP) are used as performance metrics to compare the proposed DM-DCVSL approach in static and dynamic mode with the existing static DCVSL and dynamic DCVSL designs respectively. The percentage saving in PDP varies from 20.61%-97.44% for DM-DCVSL designs. The performance of 2-input AND/NAND and XOR/XNOR gates is studied at different process corners. A maximum PDP reduction of 97.7% and 97.48% is achieved using proposed approach considering all process corners in static and dynamic mode respectively.