A Low-delay Configurable Register for FPGA

Abstract

A low-delay configurable register for FPGA is designed in this paper. This design is based on the basic master-slave D flip-flop, uses transmission gates on key nodes to control the register into four modes: register mode, latch mode, synchronous overwrite mode and asynchronous overwrite mode, then inputs desired signals to complete the functions of registers, latches, global initialization, synchronous reset, asynchronous reset, capture and write-back. The control signals and the D input are separated so that control circuit will not affect the register's timing parameters. A pre-simulation is carried out under the 28nm process and the results show that the configurable register's various functions are correct. The timing parameters are equivalent to the non-configurable master-slave D flip-flops, which proves that the control circuit does not affect the timing parameters. In this paper, configurable register has a 41-ps delay of CK to Q, a 7-ps setup time and a 0-ps hold time.