F. Oehler, J. Sauerer, R. Hagelauer, D. Seitzer, U. Nowotny, B. Raynor, J. Schneider
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引用次数: 10
Abstract
A 0.3 /spl mu/m AlGaAs-HEMT technology was used to develop a high speed analog to digital converter (ADC). The 5-b converter based on a parallel architecture, operates up to a 3.6 GHz sampling rate. Excellent dynamic performance was achieved by an optimized comparator design and careful layout of the signal and clock lines. Each comparator is preceeded by a preamplifier to enhance its sensitivity and to minimize clock kickback. Using source follower buffers at the input, a very linear input capacitance was achieved. Thus the ADC's overall input capacitance is voltage independent.<>
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