Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394496
T. Maeda, K. Numata, M. Tokushima, M. Ishikawa, M. Fukaishi, H. Hida, Y. Ohno
The authors describe a new GaAs static flip flop, called TD-FF (tri-state driver flip flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FFs so far. The authors also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.<>
{"title":"A novel high-speed low-power tri-state driver flip flop (TD-FF) for ultra-low supply voltage GaAs heterojunction FET LSIs","authors":"T. Maeda, K. Numata, M. Tokushima, M. Ishikawa, M. Fukaishi, H. Hida, Y. Ohno","doi":"10.1109/GAAS.1993.394496","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394496","url":null,"abstract":"The authors describe a new GaAs static flip flop, called TD-FF (tri-state driver flip flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value reported for D-FFs so far. The authors also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123123612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394491
W. Roesch
Improvements in semiconductor reliability are constantly being expected and so far, they have been achieved. A historical perspective is presented which provides evidence regarding changes in the way people think about reliability, for GaAs MESFET integrated circuits, in particular. Comparisons to silicon reliability history, and between old and new philosophies are made. Although not intended as a panacea, the direction towards measuring, analyzing, and controlling the variability of all input parameters to reliability is discussed as the key to reaching the next generation.<>
{"title":"GaAs IC reliability, the next generation","authors":"W. Roesch","doi":"10.1109/GAAS.1993.394491","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394491","url":null,"abstract":"Improvements in semiconductor reliability are constantly being expected and so far, they have been achieved. A historical perspective is presented which provides evidence regarding changes in the way people think about reliability, for GaAs MESFET integrated circuits, in particular. Comparisons to silicon reliability history, and between old and new philosophies are made. Although not intended as a panacea, the direction towards measuring, analyzing, and controlling the variability of all input parameters to reliability is discussed as the key to reaching the next generation.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124938309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394490
W. Yamada, K. Macwilliams, S. Brown, N. Zamani, B. Blaes, M. Buehler
The authors present the results from a study of a commercial digital GaAs foundry and attempt to establish a methodology to characterize the process, performance, and reliability of that foundry's technology. A variety of increasingly complex test structures were designed to characterize the digital GaAs process. These structures include the elemental test structures for interconnects, contacts, junctions and devices to increasingly complex gates, latches, simple circuits and gate arrays. The increasing complexity in test structures insures that the results obtained are consistent and accurate. A novel timing circuit called a matrix delay chain is one of the key structures used to characterize the technology. This test structure is intended to allow the direct measurement of inverter propagation delay and as a monitor of performance variations. These variations are due to (1) process nonuniformities, (2) power supply fluctuations, (3) temperature extremes, (4) reliability degradations and, for use in space, and (5) radiation degradations. The collection of test structures was fabricated in an enhancement-depletion mode process utilizing 0.8 /spl mu/m gate length, and three level aluminum based metallization.<>
{"title":"Process, performance, and reliability characterization of a GaAs VLSI technology","authors":"W. Yamada, K. Macwilliams, S. Brown, N. Zamani, B. Blaes, M. Buehler","doi":"10.1109/GAAS.1993.394490","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394490","url":null,"abstract":"The authors present the results from a study of a commercial digital GaAs foundry and attempt to establish a methodology to characterize the process, performance, and reliability of that foundry's technology. A variety of increasingly complex test structures were designed to characterize the digital GaAs process. These structures include the elemental test structures for interconnects, contacts, junctions and devices to increasingly complex gates, latches, simple circuits and gate arrays. The increasing complexity in test structures insures that the results obtained are consistent and accurate. A novel timing circuit called a matrix delay chain is one of the key structures used to characterize the technology. This test structure is intended to allow the direct measurement of inverter propagation delay and as a monitor of performance variations. These variations are due to (1) process nonuniformities, (2) power supply fluctuations, (3) temperature extremes, (4) reliability degradations and, for use in space, and (5) radiation degradations. The collection of test structures was fabricated in an enhancement-depletion mode process utilizing 0.8 /spl mu/m gate length, and three level aluminum based metallization.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126036630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394499
R. Oettel
The ultimate performance of an integrated circuit can be substantially improved by using a compiler-based tool for its design. This is particularly true for gallium arsenide circuits where speed performance is critical, the cost of real estate is high, and design expertise is scarce. Furthermore, now that high levels of integration are possible with GaAs, automated layout tools are needed to manage the complexity and simultaneously preserve the performance potential of the technology. The result of applying compiler methodology to several generations of gallium arsenide technology over an eight year period is reported.<>
{"title":"The use of compilers for digital GaAs IC design","authors":"R. Oettel","doi":"10.1109/GAAS.1993.394499","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394499","url":null,"abstract":"The ultimate performance of an integrated circuit can be substantially improved by using a compiler-based tool for its design. This is particularly true for gallium arsenide circuits where speed performance is critical, the cost of real estate is high, and design expertise is scarce. Furthermore, now that high levels of integration are possible with GaAs, automated layout tools are needed to manage the complexity and simultaneously preserve the performance potential of the technology. The result of applying compiler methodology to several generations of gallium arsenide technology over an eight year period is reported.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123710107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394468
W. Brinlee, A. Pavio, C. Goldsmith, W. Thompson
A unique multifunction receiver converter chip, consisting of RF amplifiers, switches, a lumped-element filter, and a double-balanced mixer, has been developed. The chip design employs various circuit design refinements, such as amplifier feedback techniques to enhance stability and repeatability, FET switches to reduce power consumption, and a lumped-element filter to reduce size. The double-balanced mixer topology eliminates IF extraction problems and combines the best performance characteristics of active and passive baluns while employing diode mixing elements.<>
{"title":"A monolithic multifunction EW broadband receiver converter","authors":"W. Brinlee, A. Pavio, C. Goldsmith, W. Thompson","doi":"10.1109/GAAS.1993.394468","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394468","url":null,"abstract":"A unique multifunction receiver converter chip, consisting of RF amplifiers, switches, a lumped-element filter, and a double-balanced mixer, has been developed. The chip design employs various circuit design refinements, such as amplifier feedback techniques to enhance stability and repeatability, FET switches to reduce power consumption, and a lumped-element filter to reduce size. The double-balanced mixer topology eliminates IF extraction problems and combines the best performance characteristics of active and passive baluns while employing diode mixing elements.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125289661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394451
D. Lo, G. Dow, S. Chen, H. Wang, T. Ton, K. Tan, B. Allen
The authors report a monolithic 1/spl times/2 W-band four-stage low noise amplifier array based on 0.1 /spl mu/m PM Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.22/Ga/sub 0.78/As/GaAs HEMT technology for applications in W-band phased array antennas or focal plane imaging array. The amplifiers have achieved an average gain of 19 dB over the band from 77 to 100 GHz and a noise figure of 5-6 dB from 92 to 96 GHz. Crosstalk between the amplifiers in the 1/spl times/2 array is less than -25 dB from 80 to 100 GHz. Successful demonstration of this high level integrated MMIC indicates the maturity of 0.1 /spl mu/m GaAs-based HEMT technology and the feasiblity of high density monolithic integration of array or multifunction chips for future low cost and compact millimeter wave systems.<>
{"title":"A monolithic 1/spl times/2 W-band four-stage low noise amplifier array [for antennas and FPA]","authors":"D. Lo, G. Dow, S. Chen, H. Wang, T. Ton, K. Tan, B. Allen","doi":"10.1109/GAAS.1993.394451","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394451","url":null,"abstract":"The authors report a monolithic 1/spl times/2 W-band four-stage low noise amplifier array based on 0.1 /spl mu/m PM Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.22/Ga/sub 0.78/As/GaAs HEMT technology for applications in W-band phased array antennas or focal plane imaging array. The amplifiers have achieved an average gain of 19 dB over the band from 77 to 100 GHz and a noise figure of 5-6 dB from 92 to 96 GHz. Crosstalk between the amplifiers in the 1/spl times/2 array is less than -25 dB from 80 to 100 GHz. Successful demonstration of this high level integrated MMIC indicates the maturity of 0.1 /spl mu/m GaAs-based HEMT technology and the feasiblity of high density monolithic integration of array or multifunction chips for future low cost and compact millimeter wave systems.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125682478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394469
A. Clei, S. Sainson, M. Feuillade, K. Sauv, R. Azoulay, J. Dumas, M. Chertouk, O. Calliger, R. Lefevre
High performance FETs and circuits realized on GaAs layers heteroepitaxially grown on InP are described. Low parasitic effects are ascertained by noise and pulse measurements indicating a low electrical activity of the defects related to the lattice mismatch. 0.3 /spl mu/m gatelength laser drivers show satisfactory behavior at 10 Gbit/s. Device degradation observed after accelerated aging tests results from contact degradation rather than from mismatched materials problems. GaAs on InP FETs appear to be good candidates for 1.3-1.55 /spl mu/m OEICs.<>
{"title":"GaAs on InP MESFETs and circuits for OEICs","authors":"A. Clei, S. Sainson, M. Feuillade, K. Sauv, R. Azoulay, J. Dumas, M. Chertouk, O. Calliger, R. Lefevre","doi":"10.1109/GAAS.1993.394469","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394469","url":null,"abstract":"High performance FETs and circuits realized on GaAs layers heteroepitaxially grown on InP are described. Low parasitic effects are ascertained by noise and pulse measurements indicating a low electrical activity of the defects related to the lattice mismatch. 0.3 /spl mu/m gatelength laser drivers show satisfactory behavior at 10 Gbit/s. Device degradation observed after accelerated aging tests results from contact degradation rather than from mismatched materials problems. GaAs on InP FETs appear to be good candidates for 1.3-1.55 /spl mu/m OEICs.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115353008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394456
Der-woei Wu, D.L. Miller, M. Fukuda, Y. Yun
A new parameter extraction technique for heterojunction bipolar transistors (HBTs) is described. Utilizing a novel low frequency extraction algorithm, the intrinsic elements and the resistive parasitics are obtained. The overall small-signal equivalent circuit of HBTs is then determined based on those extracted element values. This technique advances current equivalent circuit modeling capability of HBTs by minimizing the interactive computer optimization/simulation process and removing the need of special test structures.<>
{"title":"Unique determination of AlGaAs/GaAs HBT's small-signal equivalent circuit parameters","authors":"Der-woei Wu, D.L. Miller, M. Fukuda, Y. Yun","doi":"10.1109/GAAS.1993.394456","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394456","url":null,"abstract":"A new parameter extraction technique for heterojunction bipolar transistors (HBTs) is described. Utilizing a novel low frequency extraction algorithm, the intrinsic elements and the resistive parasitics are obtained. The overall small-signal equivalent circuit of HBTs is then determined based on those extracted element values. This technique advances current equivalent circuit modeling capability of HBTs by minimizing the interactive computer optimization/simulation process and removing the need of special test structures.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394477
N. Caglio, J. Degouy, D. Meignant, P. Rousseau, B. Leroux
An integrated GaAs FM-CW direct digital synthesizer (DDS) has been developed using Philips Microwave Limeil (PML) standard ER07AD technology. The DDS is composed of two successive functional blocks: a double phase accumulator which produces the right synchronizing sequences and a digital to analog sine converter (DASC) which generates the linear chirp waveform. The double phase accumulator has been implemented with five chips while the DASC is monolithic. The maximum measured clock frequency on the phase accumulator is 1.25 GHz and the power consumption is 320 mW. For the DASC, the maximum measured clock frequency is 1.5 GHz and the associated consumption is 600 mW.<>
{"title":"An integrated GaAs 1.25 GHz clock frequency FM-CW direct digital synthesizer","authors":"N. Caglio, J. Degouy, D. Meignant, P. Rousseau, B. Leroux","doi":"10.1109/GAAS.1993.394477","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394477","url":null,"abstract":"An integrated GaAs FM-CW direct digital synthesizer (DDS) has been developed using Philips Microwave Limeil (PML) standard ER07AD technology. The DDS is composed of two successive functional blocks: a double phase accumulator which produces the right synchronizing sequences and a digital to analog sine converter (DASC) which generates the linear chirp waveform. The double phase accumulator has been implemented with five chips while the DASC is monolithic. The maximum measured clock frequency on the phase accumulator is 1.25 GHz and the power consumption is 320 mW. For the DASC, the maximum measured clock frequency is 1.5 GHz and the associated consumption is 600 mW.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124186509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-10DOI: 10.1109/GAAS.1993.394476
S. Bar, C.S. Wu, Ming Hu, H. Kanber, C. Pao, W. Yau
The authors present an approach to establishing PHEMT manufacturing technology. They discuss the impact of development work in four key process areas. They also demonstrate good wafer uniformity and wafer to wafer reproducibility for PHEMT X-band multifunction LNAs.<>
{"title":"Manufacturing technology development for high yield pseudomorphic HEMT","authors":"S. Bar, C.S. Wu, Ming Hu, H. Kanber, C. Pao, W. Yau","doi":"10.1109/GAAS.1993.394476","DOIUrl":"https://doi.org/10.1109/GAAS.1993.394476","url":null,"abstract":"The authors present an approach to establishing PHEMT manufacturing technology. They discuss the impact of development work in four key process areas. They also demonstrate good wafer uniformity and wafer to wafer reproducibility for PHEMT X-band multifunction LNAs.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134253948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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