D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi
{"title":"Open/folded bit-line arrangement for ultra high-density DRAMs","authors":"D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi","doi":"10.1109/VLSIC.1993.920551","DOIUrl":null,"url":null,"abstract":"A new open/folded bit-line (BL) arrangement for ultra high-density DRAMs is proposed. The proposed arrangement was successfully verified by the test chip. This arrangement features a 6F/sup 2/ memory cell and relaxed sensing amplifier of 3 times the pitch of BL. The chip size with this arrangement can be reduced to 81.6% of that of the folded BL arrangement, without introducing the complicated memory cell structure and without sacrificing access speed and power dissipation. Moreover, the proposed arrangement has good array noise immunity in scaled DRAMs compared with the folded BL arrangement. This arrangement is one of the leading candidates for ultra high-density DRAMs.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920551","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 43
Abstract
A new open/folded bit-line (BL) arrangement for ultra high-density DRAMs is proposed. The proposed arrangement was successfully verified by the test chip. This arrangement features a 6F/sup 2/ memory cell and relaxed sensing amplifier of 3 times the pitch of BL. The chip size with this arrangement can be reduced to 81.6% of that of the folded BL arrangement, without introducing the complicated memory cell structure and without sacrificing access speed and power dissipation. Moreover, the proposed arrangement has good array noise immunity in scaled DRAMs compared with the folded BL arrangement. This arrangement is one of the leading candidates for ultra high-density DRAMs.
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