Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920557
D. Scott, K. Sasaki
{"title":"BiCMOS - where is the beef ?","authors":"D. Scott, K. Sasaki","doi":"10.1109/VLSIC.1993.920557","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920557","url":null,"abstract":"","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116994289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920529
B. Adams, T. Kwan
The design of an asynchronous sample-rate converter for digital audio applications is presented. Input and output sample rates are sensed automatically. The converter can be slaved to both input and output sample clocks that need not be synchronous to the chip's master clock. Sample rate ratio changes of up to 2:1 in either direction can be accommodated. Measured output SNR while driven by a 10 kHz 20-bit sine wave is 102 dB. This 200 K transistor chip is fabricated using a 0.8 /spl mu/m CMOS technology. Power dissipation is 150 mW at 16 MHz.
{"title":"A stereo asynchronous sample-rate converter for digital audio","authors":"B. Adams, T. Kwan","doi":"10.1109/VLSIC.1993.920529","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920529","url":null,"abstract":"The design of an asynchronous sample-rate converter for digital audio applications is presented. Input and output sample rates are sensed automatically. The converter can be slaved to both input and output sample clocks that need not be synchronous to the chip's master clock. Sample rate ratio changes of up to 2:1 in either direction can be accommodated. Measured output SNR while driven by a 10 kHz 20-bit sine wave is 102 dB. This 200 K transistor chip is fabricated using a 0.8 /spl mu/m CMOS technology. Power dissipation is 150 mW at 16 MHz.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123256427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920543
P. Black, T. Meng
In recent years there has been great interest in the implementation of high-speed Viterbi decoders. A potential application which has pushed decode rates into the Gb/s range is convolutional coding for optical channels. In this paper, an alternative sliding block Viterbi decoder is proposed that approaches ideal linear scaling (complexity proportional to speedup) without constraining the encoding process. Sliding block Viterbi decoder implementation of the Viterbi algorithm as a sliding block decoder (SBD) is based on the observation that the state at time n can be decoded using only the information from the interval n-L to n +L, where L is the survivor path length.
{"title":"A 1 Gb/s, 4-state, sliding block Viterbi decoder","authors":"P. Black, T. Meng","doi":"10.1109/VLSIC.1993.920543","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920543","url":null,"abstract":"In recent years there has been great interest in the implementation of high-speed Viterbi decoders. A potential application which has pushed decode rates into the Gb/s range is convolutional coding for optical channels. In this paper, an alternative sliding block Viterbi decoder is proposed that approaches ideal linear scaling (complexity proportional to speedup) without constraining the encoding process. Sliding block Viterbi decoder implementation of the Viterbi algorithm as a sliding block decoder (SBD) is based on the observation that the state at time n can be decoded using only the information from the interval n-L to n +L, where L is the survivor path length.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122316647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920532
T. Sakata, K. Itoh, M. Horiguchi, M. Aoki
Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.
{"title":"Subthreshold-current reduction circuits for multi-gigabit DRAM's","authors":"T. Sakata, K. Itoh, M. Horiguchi, M. Aoki","doi":"10.1109/VLSIC.1993.920532","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920532","url":null,"abstract":"Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123387741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920560
A. Umezawa, S. Atsumi, M. Kuriyama, H. Banba, C. Hoshino, K. Naruke, S. Yamada, Y. Ohshima, M. Oshikiri, Y. Hiura, T. Suzuki, K. Yoshikawa
A newly developed refresh scheme is introduced in a 16-Mb flash EEPROM. By providing each refresh block with its own nonvolatile element, excessive voltage stress of the flag element can be eliminated during the erase/program cycling. A small sector erase can be realized in the 16-Mb flash memory with this scheme. The EEPROM is realised in a 0.6 /spl mu/m single-metal triple-well CMOS process technology.
{"title":"A new self-data-refresh scheme for a sector erasable 16-Mb flash EEPROM","authors":"A. Umezawa, S. Atsumi, M. Kuriyama, H. Banba, C. Hoshino, K. Naruke, S. Yamada, Y. Ohshima, M. Oshikiri, Y. Hiura, T. Suzuki, K. Yoshikawa","doi":"10.1109/VLSIC.1993.920560","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920560","url":null,"abstract":"A newly developed refresh scheme is introduced in a 16-Mb flash EEPROM. By providing each refresh block with its own nonvolatile element, excessive voltage stress of the flag element can be eliminated during the erase/program cycling. A small sector erase can be realized in the 16-Mb flash memory with this scheme. The EEPROM is realised in a 0.6 /spl mu/m single-metal triple-well CMOS process technology.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115743252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920556
K. Asada, W. Bidermann, R. Brodersen
Summary form only given, as follows. The requirements of portability are driving the power supply voltages ever lower. In order to retain performance, it is desirable to lower the thershold voltage which is ultimately limited by subthreshold conduction. A variety of circuit and process voltage operation. technology design solutions to this problem will be discussed including such techniques as direct sensing of subthreshold current, series resistance, switched supplies as well as process optimization for low voltage operation.
{"title":"Ultra low power circuit design and technology","authors":"K. Asada, W. Bidermann, R. Brodersen","doi":"10.1109/VLSIC.1993.920556","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920556","url":null,"abstract":"Summary form only given, as follows. The requirements of portability are driving the power supply voltages ever lower. In order to retain performance, it is desirable to lower the thershold voltage which is ultimately limited by subthreshold conduction. A variety of circuit and process voltage operation. technology design solutions to this problem will be discussed including such techniques as direct sensing of subthreshold current, series resistance, switched supplies as well as process optimization for low voltage operation.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116356323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920528
E. Komoto, T. Homma, T. Nakamura
A JPEG compliant Huffman decoder circuit has been developed. The circuit executes at 27 MHz in order to maintain image data transfer at CCIR 601 video rates. The circuit detects and decodes variable length Huffman codes in a single clock cycle by searching among all Huffman codes in the current table. The circuit utilizes a CAM with mask bits to perform this rapid search. The architecture also utilizes a double barrel shifter to window the next portion of the input bit stream to be examined, which makes the critical path as short as possible. According to the simulation results, the delay of execution in a cycle is 18.1 ns. The total memory size is 15K bits.
{"title":"A high-speed and compact-size JPEG Huffman decoder using CAM","authors":"E. Komoto, T. Homma, T. Nakamura","doi":"10.1109/VLSIC.1993.920528","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920528","url":null,"abstract":"A JPEG compliant Huffman decoder circuit has been developed. The circuit executes at 27 MHz in order to maintain image data transfer at CCIR 601 video rates. The circuit detects and decodes variable length Huffman codes in a single clock cycle by searching among all Huffman codes in the current table. The circuit utilizes a CAM with mask bits to perform this rapid search. The architecture also utilizes a double barrel shifter to window the next portion of the input bit stream to be examined, which makes the critical path as short as possible. According to the simulation results, the delay of execution in a cycle is 18.1 ns. The total memory size is 15K bits.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123424883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920541
S. Fujita, N. Yuhki, S. Hino, Y. Arai, Y. Akazawa
A new LSI configuration is proposed for multigigabit optical interconnections with a view to low-cost, low-power-dissipation, and precise-adjustment-free interconnection modules. This configuration is based on (a) minimization of additional functions for the optical transmitter and receiver and (b) realization of fully digital automatic timing adjustment. Test fabrication results of the transmitter and receiver LSIs, and modules show the effect of this new configuration, that is, a 2.8-Gbit/s operation at a received power of -9 dBm through a 100-m optical fiber.
{"title":"Multigigabit optical interconnection LSIs","authors":"S. Fujita, N. Yuhki, S. Hino, Y. Arai, Y. Akazawa","doi":"10.1109/VLSIC.1993.920541","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920541","url":null,"abstract":"A new LSI configuration is proposed for multigigabit optical interconnections with a view to low-cost, low-power-dissipation, and precise-adjustment-free interconnection modules. This configuration is based on (a) minimization of additional functions for the optical transmitter and receiver and (b) realization of fully digital automatic timing adjustment. Test fabrication results of the transmitter and receiver LSIs, and modules show the effect of this new configuration, that is, a 2.8-Gbit/s operation at a received power of -9 dBm through a 100-m optical fiber.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128416484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920552
J. Ahn, T. H. Kim, S. M. Park, S. H. Wang, H. Lee
A new bit line organization, called Bidirectional Matched Global Bit Line (BMGB) scheme, is designed to overcome the difficulties in layout implementation and the high susceptibility to noise of conventional open bit line structure. In this scheme, the local bit line pairs are placed close to each other and well-balanced folded bit line type global bit lines are used. Measured results from a test chip, processed with 0.35 /spl mu/m technology, shows that cell array size can be reduced about 15%, while a similar performance is obtained to that of a conventional folded bit line architecture. This scheme can also be used with folded type local bit lines.
{"title":"Bidirectional matched global bit line scheme for high density DRAMs","authors":"J. Ahn, T. H. Kim, S. M. Park, S. H. Wang, H. Lee","doi":"10.1109/VLSIC.1993.920552","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920552","url":null,"abstract":"A new bit line organization, called Bidirectional Matched Global Bit Line (BMGB) scheme, is designed to overcome the difficulties in layout implementation and the high susceptibility to noise of conventional open bit line structure. In this scheme, the local bit line pairs are placed close to each other and well-balanced folded bit line type global bit lines are used. Measured results from a test chip, processed with 0.35 /spl mu/m technology, shows that cell array size can be reduced about 15%, while a similar performance is obtained to that of a conventional folded bit line architecture. This scheme can also be used with folded type local bit lines.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128735486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-05-19DOI: 10.1109/VLSIC.1993.920526
J. Fattaruso, S. Mahant-Shetti, J. B. Barton
This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. Simulations predict a computation time for the array of about 2 /spl mu/sec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 bits. The completed chip measures 7 mm by 10 mm in a 0.8 /spl mu/m CMOS technology, and is currently undergoing preliminary testing.
该模数混合模糊逻辑推理处理器芯片在32条规则的知识库上并行计算推理结果。模拟预测该阵列的计算时间约为2 /spl mu/sec。处理器接口的行为类似于静态RAM，但内部计算在模拟域中执行，预期精度为6位。完成的芯片尺寸为7mm × 10mm，采用0.8 /spl μ m CMOS技术，目前正在进行初步测试。
{"title":"A fuzzy logic inference processor","authors":"J. Fattaruso, S. Mahant-Shetti, J. B. Barton","doi":"10.1109/VLSIC.1993.920526","DOIUrl":"https://doi.org/10.1109/VLSIC.1993.920526","url":null,"abstract":"This mixed analog-digital fuzzy logic inference processor chip calculates the result of an inference over a 32-rule knowledge base in parallel. Simulations predict a computation time for the array of about 2 /spl mu/sec. The processor interface behaves like a static RAM, but internal computation is performed in the analog domain to an expected precision of 6 bits. The completed chip measures 7 mm by 10 mm in a 0.8 /spl mu/m CMOS technology, and is currently undergoing preliminary testing.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129041208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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