{"title":"RISC-V processors design: a methodology for cores development","authors":"A. Barriga","doi":"10.1109/DCIS51330.2020.9268639","DOIUrl":null,"url":null,"abstract":"This communication describes a design methodology that facilitates the implementation of processors based on the ISA of RISC-V. As an example of application of the proposed methodology, the design of three processors with different architectures and features is described.","PeriodicalId":186963,"journal":{"name":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"104 8","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DCIS51330.2020.9268639","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This communication describes a design methodology that facilitates the implementation of processors based on the ISA of RISC-V. As an example of application of the proposed methodology, the design of three processors with different architectures and features is described.
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