{"title":"A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling","authors":"M. Kaneko","doi":"10.1145/2742060.2742073","DOIUrl":null,"url":null,"abstract":"Temperature is one of the major sources of delay variations which may cause timing violations. In this paper, an approach to temperature aware clock skew scheduling for a general class of sequential circuits is proposed. At first, an alternative interpretation of the affine type (linear model) of temperature dependency is shown, which is not merely a \"linearized\" model applicable to a limited temperature range, but it can cover a class of nonlinear temperature dependency, and hence its applicability is not limited in temperature range. After that, a graph-theoretic skew scheduling considering the lower and the upper temperature bounds, which can work in a polynomial time complexity with respect to the circuit size, is derived. This framework can be applicable to the variants of temperature aware optimizations, such as maximizing upper temperature bound, maximizing clock frequency under a given temperature range, etc. Experiments using ISCAS'89 benchmark circuits show us that our approach achieves maximum 70% improvement in the upper temperature range (in a linear temperature scale) compared with a conventional skew scheduling which maximizes the minimum timing slack.","PeriodicalId":255133,"journal":{"name":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 25th edition on Great Lakes Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/2742060.2742073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Temperature is one of the major sources of delay variations which may cause timing violations. In this paper, an approach to temperature aware clock skew scheduling for a general class of sequential circuits is proposed. At first, an alternative interpretation of the affine type (linear model) of temperature dependency is shown, which is not merely a "linearized" model applicable to a limited temperature range, but it can cover a class of nonlinear temperature dependency, and hence its applicability is not limited in temperature range. After that, a graph-theoretic skew scheduling considering the lower and the upper temperature bounds, which can work in a polynomial time complexity with respect to the circuit size, is derived. This framework can be applicable to the variants of temperature aware optimizations, such as maximizing upper temperature bound, maximizing clock frequency under a given temperature range, etc. Experiments using ISCAS'89 benchmark circuits show us that our approach achieves maximum 70% improvement in the upper temperature range (in a linear temperature scale) compared with a conventional skew scheduling which maximizes the minimum timing slack.