Theoretical study of on-chip meander line resistor to improve Q-factor

Abstract

In this paper, the theoretical configuration geometry of the layout on-chip meander line resistor was studied and investigated. Various simulation of the geometric design on-chip resistor in a range Giga Hertz frequency are performed. The effect of the quality factor of each design geometry of meander line resistor on high frequency operation was in deep studied and discussed. Besides, parameter extraction geometry of this on-chip meander line resistor was introduced. As a result, the parameter line length (h), line segment (N) and then following by spacing (d) and width (w), which are playing an important role on designing the geometry layout to improve the Q-factor. Throughout the scaling graphical method, it has been granted out optimize value combination of parameter by improving almost 70% of Q-factor and loss of resistance less than 17% of the nominal design. The result of the Design optimization configuration has low Q-factor when compared with a nominal Design nominal configuration. This is because of the large value of number segment (N) and smaller numbers of line length (h), which has less coupling effect and less resistivity effect. All result base on mathematics computation data was discussed and performed.