Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920810
N. Burham, A. A. Hamzah, B. Y. Majlis
Silicon is a promising material due to it having reliable and desirable characteristics for making porous silicon membrane. Porous membrane is widely used in various applications especially in bioMEMS, Lab on Chip and MEMS. Normally, porous membrane functions as a part of filtration system that can be integrated with other systems to make a complete device. The porous silicon membrane is simulated using COMSOL 4.3a for mechanical verification. This work compares the simulation result of the silicon membrane design with theoretical calculation. This paper studies the effect of pressure across the silicon membrane based on the deflection and von Mises stress at the centre of silicon membrane. The maximum deflection and von Mises stress of different membrane thickness and pore shapes are compared against various levels of pressure applied on the silicon membrane surface. The 100 nm thin silicon membrane studied was found to be far superior to the 25 nm silicon thin membrane, being able to mechanically withstand the applied pressure up to 7.33 kPa (55 mmHg).
{"title":"Mechanical characteristics of porous silicon membrane for filtration in artificial kidney","authors":"N. Burham, A. A. Hamzah, B. Y. Majlis","doi":"10.1109/SMELEC.2014.6920810","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920810","url":null,"abstract":"Silicon is a promising material due to it having reliable and desirable characteristics for making porous silicon membrane. Porous membrane is widely used in various applications especially in bioMEMS, Lab on Chip and MEMS. Normally, porous membrane functions as a part of filtration system that can be integrated with other systems to make a complete device. The porous silicon membrane is simulated using COMSOL 4.3a for mechanical verification. This work compares the simulation result of the silicon membrane design with theoretical calculation. This paper studies the effect of pressure across the silicon membrane based on the deflection and von Mises stress at the centre of silicon membrane. The maximum deflection and von Mises stress of different membrane thickness and pore shapes are compared against various levels of pressure applied on the silicon membrane surface. The 100 nm thin silicon membrane studied was found to be far superior to the 25 nm silicon thin membrane, being able to mechanically withstand the applied pressure up to 7.33 kPa (55 mmHg).","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124408579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920826
Qahtan Khalaf Omran, M. Islam, N. Misran, M. Faruque
A direct digital frequency synthesizer (DDFS) based on piecewise linear approximation method is presented in this paper. The proposed method allows sequential read access to memory cells per one clock cycle using time sharing. The output values will be momentarily stowed and read at a later time; thereby the slope is simply derived from these sinusoid points at successive phase angles. As a consequence, the DDFS only needs to store fewer coefficients and the hardware complexity is significantly shortened. The proposed DDFS has been analyzed using MATLAB Simulink and examined over entire Nyquist frequency band. The simulation results show a promising result of 84 dBc spurious free dynamic range (SFDR). The resultant low complexity architecture along with high spectral purity synthesized signal meets the specifications of recent portable battery-driven products.
{"title":"An efficient ROM compression technique for linear- interpolated direct digital frequency synthesizer","authors":"Qahtan Khalaf Omran, M. Islam, N. Misran, M. Faruque","doi":"10.1109/SMELEC.2014.6920826","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920826","url":null,"abstract":"A direct digital frequency synthesizer (DDFS) based on piecewise linear approximation method is presented in this paper. The proposed method allows sequential read access to memory cells per one clock cycle using time sharing. The output values will be momentarily stowed and read at a later time; thereby the slope is simply derived from these sinusoid points at successive phase angles. As a consequence, the DDFS only needs to store fewer coefficients and the hardware complexity is significantly shortened. The proposed DDFS has been analyzed using MATLAB Simulink and examined over entire Nyquist frequency band. The simulation results show a promising result of 84 dBc spurious free dynamic range (SFDR). The resultant low complexity architecture along with high spectral purity synthesized signal meets the specifications of recent portable battery-driven products.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123409720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920898
I. Saurdi, A. Shafura, M. H. Mamat, M. Rusop
In this work, the aligned ZnO Nanorod were grown on ITO-coated glass substrates with Sn-doped ZnO films as a seed layer at different zinc acetate solution molarities of 0.05M, 0.04M, 0.03M and 0.02M by Sol gel immersion ultrasonic assisted. The aligned ZnO nanorods grown at different solution molarities had different of diameter and interspaces between nanorod. The ZnO nanorod grown at 0.03M Zinc acetate exhibits high surface area, whereby bigger interspaces between nanorod and had smaller of nanorod diameter. The nanorod grown at 0.05M had bigger of nanorod diameter and slightly lower of surface area as compared to nanorod grown at 0.03M. Meanwhile, the nanorod grown at 0.02M shows a scattered of nanorod growth with low surface area and lesser density. From the solar simulator measurement the solar energy conversion efficiency (η) of 0.989% under AM 1.5 was obtained for 0.03M aligned ZnO nanorod photoanode DSSC, which higher than other ZnO nanorod photoanode. The improvement which was due to higher surface area of smaller diameter nanorod that had bigger interspaces between nanorod for better dye absorption.
{"title":"Dye-sensitized solar cell using aligned ZnO nanorod grown on SZO films at different solution molarities","authors":"I. Saurdi, A. Shafura, M. H. Mamat, M. Rusop","doi":"10.1109/SMELEC.2014.6920898","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920898","url":null,"abstract":"In this work, the aligned ZnO Nanorod were grown on ITO-coated glass substrates with Sn-doped ZnO films as a seed layer at different zinc acetate solution molarities of 0.05M, 0.04M, 0.03M and 0.02M by Sol gel immersion ultrasonic assisted. The aligned ZnO nanorods grown at different solution molarities had different of diameter and interspaces between nanorod. The ZnO nanorod grown at 0.03M Zinc acetate exhibits high surface area, whereby bigger interspaces between nanorod and had smaller of nanorod diameter. The nanorod grown at 0.05M had bigger of nanorod diameter and slightly lower of surface area as compared to nanorod grown at 0.03M. Meanwhile, the nanorod grown at 0.02M shows a scattered of nanorod growth with low surface area and lesser density. From the solar simulator measurement the solar energy conversion efficiency (η) of 0.989% under AM 1.5 was obtained for 0.03M aligned ZnO nanorod photoanode DSSC, which higher than other ZnO nanorod photoanode. The improvement which was due to higher surface area of smaller diameter nanorod that had bigger interspaces between nanorod for better dye absorption.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"7 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128377094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920837
Z. Aznilinda, M. Ramly, N. Kamarozaman, S. H. Herman
This paper demonstrates the fabrication method and reports the essential physical characterization of a memristive device with TiO2 or titania as an active layer. The memristive device was fabricated on glass substrate. Titania thin films were grown in two layers by RF-magnetron sputtering technique onto the substrates. The first layer is a titania layer etched by 1% HF (Hydrofluoric acid) before the deposition of the second layer. The etching time was varied; for 5 seconds and 7 seconds. Current-voltage (I-V) curves of the samples were measured from the voltage loop ranging from 0V to -5V, -5V to 5V then back to 0V and also from -5V to 5V then back to -5V. It was proven that the HF-etch give an improvement in the memristive behavior when it is etched at 7 s.
{"title":"Memristive behavior of HF-etched sputtered titania thin films","authors":"Z. Aznilinda, M. Ramly, N. Kamarozaman, S. H. Herman","doi":"10.1109/SMELEC.2014.6920837","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920837","url":null,"abstract":"This paper demonstrates the fabrication method and reports the essential physical characterization of a memristive device with TiO2 or titania as an active layer. The memristive device was fabricated on glass substrate. Titania thin films were grown in two layers by RF-magnetron sputtering technique onto the substrates. The first layer is a titania layer etched by 1% HF (Hydrofluoric acid) before the deposition of the second layer. The etching time was varied; for 5 seconds and 7 seconds. Current-voltage (I-V) curves of the samples were measured from the voltage loop ranging from 0V to -5V, -5V to 5V then back to 0V and also from -5V to 5V then back to -5V. It was proven that the HF-etch give an improvement in the memristive behavior when it is etched at 7 s.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129799940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920802
N. Othman, M. Arshad, S. Hashim
In this work, we investigate the impact of different ground planes of UTBB SOI MOSFETs under the single-gate (SG) and double-gate (DG) operation modes by numerical simulations. Simulations were performed for 10 nm gate length UTBB SOI MOSFET of 7 nm thin body (Tsi) and 10 nm thin buried oxide (TBOX) for Vd = 20 mV and 1.0 V. For DG operation mode, the back-gate (BG) and front-gate (FG) were swept simultaneously from 0 to 1.5 V with 10 mV incremental steps. Results reported are on key device parameters such as the threshold voltage (Vth), drain induced barrier lowering (DIBL), drive current (Ion), subthreshold swing (SS) and transconductance (gm). Ground Plane (GP) - B structure which employed a p+ doping under the channel shows the best results under the DG operation mode in terms of the lowest DIBL and SS. However, it recorded a slightly higher Vth while the results of Ion and gm are comparable with its other GP counterparts.
在这项工作中，我们通过数值模拟研究了在单栅极(SG)和双栅极(DG)工作模式下，不同地平面对UTBB SOI mosfet的影响。对7 nm薄体(Tsi)和10 nm薄埋氧化物(TBOX)的10 nm栅极长度UTBB SOI MOSFET在Vd = 20 mV和1.0 V下进行了模拟。对于DG工作模式，后门(BG)和前门(FG)同时以10 mV的增量步长从0到1.5 V扫频。结果报告了关键器件参数，如阈值电压(Vth)，漏极诱导势垒降低(DIBL)，驱动电流(Ion)，亚阈值摆幅(SS)和跨导(gm)。在通道下掺杂p+的地平面(GP) - B结构在DG工作模式下的DIBL和SS最低，但其Vth略高，而离子和gm的结果与其他GP结构相当。
{"title":"Impact of different ground planes of UTBB SOI MOSFETs under the single-gate (SG) and double-gate (DG) operation mode","authors":"N. Othman, M. Arshad, S. Hashim","doi":"10.1109/SMELEC.2014.6920802","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920802","url":null,"abstract":"In this work, we investigate the impact of different ground planes of UTBB SOI MOSFETs under the single-gate (SG) and double-gate (DG) operation modes by numerical simulations. Simulations were performed for 10 nm gate length UTBB SOI MOSFET of 7 nm thin body (Tsi) and 10 nm thin buried oxide (TBOX) for Vd = 20 mV and 1.0 V. For DG operation mode, the back-gate (BG) and front-gate (FG) were swept simultaneously from 0 to 1.5 V with 10 mV incremental steps. Results reported are on key device parameters such as the threshold voltage (Vth), drain induced barrier lowering (DIBL), drive current (Ion), subthreshold swing (SS) and transconductance (gm). Ground Plane (GP) - B structure which employed a p+ doping under the channel shows the best results under the DG operation mode in terms of the lowest DIBL and SS. However, it recorded a slightly higher Vth while the results of Ion and gm are comparable with its other GP counterparts.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123671993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920880
A. H. Azman, R. Ayub, M. Arshad, S. Norhafiezah, M. Fathil, M. Z. Kamarudin, M. Nurfaiz, U. Hashim
The continuing trend toward miniaturization of silicon devices is enforcing development of ultra-thin dielectrics. While the thermally grown SiO2 has been used as a gate dielectric ever since the decade of silicon device began, it appears that the electrical and physical properties of pure SiO2 are not good enough to provide acceptable for ultra-thin gate dielectric film. There are many available methods to control the ultra-thin film; In this paper we show a simple but promising method that incorporated nitrogen as a second gas in the dry oxidation process, on which the growth rate can be controlled. This method produce surface protective layers against impurity penetration, good interfacial characteristics and strengthens the oxide structure, which directly related to improvement the gate dielectric quality.
{"title":"Controlling growth rate of ultra-thin Silicon Dioxide layer by incorporating nitrogen gas during dry thermal oxidation","authors":"A. H. Azman, R. Ayub, M. Arshad, S. Norhafiezah, M. Fathil, M. Z. Kamarudin, M. Nurfaiz, U. Hashim","doi":"10.1109/SMELEC.2014.6920880","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920880","url":null,"abstract":"The continuing trend toward miniaturization of silicon devices is enforcing development of ultra-thin dielectrics. While the thermally grown SiO2 has been used as a gate dielectric ever since the decade of silicon device began, it appears that the electrical and physical properties of pure SiO2 are not good enough to provide acceptable for ultra-thin gate dielectric film. There are many available methods to control the ultra-thin film; In this paper we show a simple but promising method that incorporated nitrogen as a second gas in the dry oxidation process, on which the growth rate can be controlled. This method produce surface protective layers against impurity penetration, good interfacial characteristics and strengthens the oxide structure, which directly related to improvement the gate dielectric quality.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"36 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113971063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920804
M. S. N. Humaira, Uda Hashim, T. Nazwa, S. T. Ten, Shahab Ahmad, Nor Azah Yusof
A recent breakthrough in nanotechnology provides a great extent in sensor fabrication and application. The technology has emerged as a powerful technique to minimize the size of devices; amount of materials, energy and time consumption. Nanogap based sensor is one of the sensor that capable of characterizing and quantifying molecules selectively and sensitively with good electrical behavior. In this manuscript, we present a collaboration work between UniMAP, MARDI and UPM in the process development of 40 nm silicon nanogap for sensor application. The process consists of a combination of electron beam lithography (EBL) method and conventional photolithography method. Both methods were for nanogap and electrodes pattern respectively. Silicon on insulator (SOI) substrate was used to fabricate the nanogap structure and gold was used for the electrode. The ability of EBL system to fabricate a gap in nanometer scale with direct lithography technique on SOI substrate gives advantages in this development work. The developed silicon nanogap device was physically characterized with scanning electron microscope (SEM). The sensor application was accomplished by testing the device with different level of pH solutions using a dielectric analyzer.
{"title":"Process development of 40 nm silicon nanogap for sensor application","authors":"M. S. N. Humaira, Uda Hashim, T. Nazwa, S. T. Ten, Shahab Ahmad, Nor Azah Yusof","doi":"10.1109/SMELEC.2014.6920804","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920804","url":null,"abstract":"A recent breakthrough in nanotechnology provides a great extent in sensor fabrication and application. The technology has emerged as a powerful technique to minimize the size of devices; amount of materials, energy and time consumption. Nanogap based sensor is one of the sensor that capable of characterizing and quantifying molecules selectively and sensitively with good electrical behavior. In this manuscript, we present a collaboration work between UniMAP, MARDI and UPM in the process development of 40 nm silicon nanogap for sensor application. The process consists of a combination of electron beam lithography (EBL) method and conventional photolithography method. Both methods were for nanogap and electrodes pattern respectively. Silicon on insulator (SOI) substrate was used to fabricate the nanogap structure and gold was used for the electrode. The ability of EBL system to fabricate a gap in nanometer scale with direct lithography technique on SOI substrate gives advantages in this development work. The developed silicon nanogap device was physically characterized with scanning electron microscope (SEM). The sensor application was accomplished by testing the device with different level of pH solutions using a dielectric analyzer.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114835112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920884
A. Dehzangi, F. Larki, B. Majlis, Zainab Kazemi, M. Ariannejad, N. Khalilzadeh
Atomic force microscopy nanolithography (AFM) is a strong fabrication method for micro and nano structure due to its high spatial resolution and positioning abilities. Mixing AFM nanolithography with advantage of silicon-on-insulator (SOI) technology provides the opportunity to achieve more reliable Si nanostructures. In this letter, we try to investigate the reproducibility of AFM base nanolithography for fabrication of the micro/nano structures. In this matter local anodic oxidation (LAO) procedure applied to pattern a silicon nanostructure on p-type (1015 cm-3) SOI using AFM base nanolithography. Then chemical etching is applied, as potassium hydroxide (saturated with isopropyl alcohol) and hydrofluoric etching for removing of Si and oxide layer, respectively. All parameters contributed in fabrication process were optimized and the final results revealed a good potential for using AFM base nanolithography in order to get a reproducible method of fabrication.
{"title":"Atomic force microscope base nanolithography for reproducible micro and nanofabrication","authors":"A. Dehzangi, F. Larki, B. Majlis, Zainab Kazemi, M. Ariannejad, N. Khalilzadeh","doi":"10.1109/SMELEC.2014.6920884","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920884","url":null,"abstract":"Atomic force microscopy nanolithography (AFM) is a strong fabrication method for micro and nano structure due to its high spatial resolution and positioning abilities. Mixing AFM nanolithography with advantage of silicon-on-insulator (SOI) technology provides the opportunity to achieve more reliable Si nanostructures. In this letter, we try to investigate the reproducibility of AFM base nanolithography for fabrication of the micro/nano structures. In this matter local anodic oxidation (LAO) procedure applied to pattern a silicon nanostructure on p-type (1015 cm-3) SOI using AFM base nanolithography. Then chemical etching is applied, as potassium hydroxide (saturated with isopropyl alcohol) and hydrofluoric etching for removing of Si and oxide layer, respectively. All parameters contributed in fabrication process were optimized and the final results revealed a good potential for using AFM base nanolithography in order to get a reproducible method of fabrication.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124338904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920916
S. Hatta, N. Soin, S. H. Abdul Rahman, Y. A. Wahab, H. Hussin
The rapid scaling of the CMOS technology is causing the evaluation from conventional planar MOSFETs to the FinFET architecture, particularly in the 22 nm and 14 nm technology nodes. FinFETs technologies ensure low power usage and better area utilization, as well as traditional scaling improvements. It was observed that for FinFETs, the smaller the width of the fin, the better the characteristics. It was observed that drain current characteristics of the NFinFET and PFinFET at both the linear and saturation regime would decrease in magnitude as the width of the fin was decreased. The Ion/Ioff ratio generally decreases as the width of the fin increases. The NFinFET particularly exhibits a significant drop in the Ion/Ioff of to nearly 50% for a change of fin width from 5nm to 15nm.
{"title":"Effects of the fin width variation on the performance of 16 nm FinFETs with round fin corners and tapered fin shape","authors":"S. Hatta, N. Soin, S. H. Abdul Rahman, Y. A. Wahab, H. Hussin","doi":"10.1109/SMELEC.2014.6920916","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920916","url":null,"abstract":"The rapid scaling of the CMOS technology is causing the evaluation from conventional planar MOSFETs to the FinFET architecture, particularly in the 22 nm and 14 nm technology nodes. FinFETs technologies ensure low power usage and better area utilization, as well as traditional scaling improvements. It was observed that for FinFETs, the smaller the width of the fin, the better the characteristics. It was observed that drain current characteristics of the NFinFET and PFinFET at both the linear and saturation regime would decrease in magnitude as the width of the fin was decreased. The Ion/Ioff ratio generally decreases as the width of the fin increases. The NFinFET particularly exhibits a significant drop in the Ion/Ioff of to nearly 50% for a change of fin width from 5nm to 15nm.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131473505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920883
Y. Ang, M. Arshad, K. L. Foo, Md N. M. Nuzaihan, A. H. Azman, U. Hashim
We present the fabrication and electrical characterization of polysilicon and their properties with application in biomolecule sensors for DNA detection. Conventional photolithography technique was used to fabricate the DNA detection structure for two different wafer substrate i.e. N- and P-type. The fabrication processes involve of deposition, etching and oxidation to achieve the final structure. Surface modification, immobilization and hybridization were executed prior to electrical characterization by using cyclic voltammetry. It was observed that the modified surface with APTES achieved the highest current for both p- and n-type wafer with changes from 0.52 μA to 3.32 μA and from 0.57 μA to 2.52 μA respectively. Moreover, redox current of hybridization is observed approximately 22 % and 10 % larger than immobilized electrode for p- and n-type wafer.
{"title":"Fabrication and characterization of polysilicon for DNA detection","authors":"Y. Ang, M. Arshad, K. L. Foo, Md N. M. Nuzaihan, A. H. Azman, U. Hashim","doi":"10.1109/SMELEC.2014.6920883","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920883","url":null,"abstract":"We present the fabrication and electrical characterization of polysilicon and their properties with application in biomolecule sensors for DNA detection. Conventional photolithography technique was used to fabricate the DNA detection structure for two different wafer substrate i.e. N- and P-type. The fabrication processes involve of deposition, etching and oxidation to achieve the final structure. Surface modification, immobilization and hybridization were executed prior to electrical characterization by using cyclic voltammetry. It was observed that the modified surface with APTES achieved the highest current for both p- and n-type wafer with changes from 0.52 μA to 3.32 μA and from 0.57 μA to 2.52 μA respectively. Moreover, redox current of hybridization is observed approximately 22 % and 10 % larger than immobilized electrode for p- and n-type wafer.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133808435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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