Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow

K. Renterghem, Pieter Demuytere, D. Verhulst, J. Vandewege, X. Qiu
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引用次数: 3

Abstract

In this paper we research an FPGA based application specific instruction set processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a fully optimized ASIP with a VLIW instruction set which allows for high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment
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利用可重定向编译流开发一种支持以太网访问流的ASIP
本文研究了一种基于FPGA的应用专用指令集处理器(ASIP),该处理器使用可重定向编译流来满足流感知以太网接入节点的需求。该工具链用于开发初始处理器设计,评估性能并识别潜在瓶颈。第二次设计迭代产生了一个完全优化的带有VLIW指令集的ASIP,该指令集允许ASIP内部功能单元之间的高度并行,并具有专用指令来加速典型的数据包处理任务。这样,单个处理器就能够处理千兆以太网链路的全部吞吐量。为了达到10gbit /s以太网接入节点的目标,多个处理器在多核环境中并行运行
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