OPTIMISATION OF THE GATE VOLTAGE IN SiC MOSFETS: EFFICIENCY VS RELIABILITY

J. Ortiz-Gonzalez, R. Wu, Haimeng Wu, Xiang Wang, Volker Pickert, Philip A. Mawby, O. Alatise
{"title":"OPTIMISATION OF THE GATE VOLTAGE IN SiC MOSFETS: EFFICIENCY VS RELIABILITY","authors":"J. Ortiz-Gonzalez, R. Wu, Haimeng Wu, Xiang Wang, Volker Pickert, Philip A. Mawby, O. Alatise","doi":"10.1049/icp.2021.1043","DOIUrl":null,"url":null,"abstract":"This paper presents a comprehensive study of the impact of the gate voltage on the switching and ON-state performance of SiC MOSFETs. It is well known that the gate oxide in SiC MOSFETs is not as reliable as that in silicon MOSFETs due to increased fixed oxide and interface traps. Numerous studies have shown reduced performance on time-dependent dielectric breakdown (TDDB) and oxide robustness in SiC MOSFETs compared to silicon devices. On the one hand, a high ON-state gate-source voltage VGS is required for proper channel inversion, low ON-state loss and fast switching while on the other hand, a lower ONstate VGS reduces the electrical stress on the gate oxide and improves long term reliability. Understanding the implications of the selected gate voltage on the operation of the power device will be fundamental for achieving an optimal balance between electrical performance and gate oxide reliability. This paper shows that reducing the maximum gate driver supply voltage VGG only affects turn-ON losses while turn-OFF losses are independent of VGG. The experimental characterisation is complemented with electrothermal simulations to evaluate the impact of the gate voltage on the operation of a converter. The paper shows that reducing VGG by 10% causes an increase of 7.6% in the device losses and 1.4 °C in junction temperature in simulated converter operation. Furthermore, if the switching speed is increased by means of reducing the gate resistance, the impact of the conduction losses can be compensated. These results are fundamental for balancing system efficiency and reliability in SiC MOSFETs.","PeriodicalId":188371,"journal":{"name":"The 10th International Conference on Power Electronics, Machines and Drives (PEMD 2020)","volume":"24 7","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 10th International Conference on Power Electronics, Machines and Drives (PEMD 2020)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/icp.2021.1043","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

This paper presents a comprehensive study of the impact of the gate voltage on the switching and ON-state performance of SiC MOSFETs. It is well known that the gate oxide in SiC MOSFETs is not as reliable as that in silicon MOSFETs due to increased fixed oxide and interface traps. Numerous studies have shown reduced performance on time-dependent dielectric breakdown (TDDB) and oxide robustness in SiC MOSFETs compared to silicon devices. On the one hand, a high ON-state gate-source voltage VGS is required for proper channel inversion, low ON-state loss and fast switching while on the other hand, a lower ONstate VGS reduces the electrical stress on the gate oxide and improves long term reliability. Understanding the implications of the selected gate voltage on the operation of the power device will be fundamental for achieving an optimal balance between electrical performance and gate oxide reliability. This paper shows that reducing the maximum gate driver supply voltage VGG only affects turn-ON losses while turn-OFF losses are independent of VGG. The experimental characterisation is complemented with electrothermal simulations to evaluate the impact of the gate voltage on the operation of a converter. The paper shows that reducing VGG by 10% causes an increase of 7.6% in the device losses and 1.4 °C in junction temperature in simulated converter operation. Furthermore, if the switching speed is increased by means of reducing the gate resistance, the impact of the conduction losses can be compensated. These results are fundamental for balancing system efficiency and reliability in SiC MOSFETs.
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SiC mosfet中栅极电压的优化:效率与可靠性
本文全面研究了栅极电压对SiC mosfet开关和导通性能的影响。众所周知,由于固定氧化物和界面陷阱的增加,SiC mosfet中的栅极氧化物不如硅mosfet中的栅极氧化物可靠。大量研究表明,与硅器件相比,SiC mosfet的时间相关介电击穿(TDDB)性能和氧化物稳健性降低。一方面,高导通状态栅源电压VGS需要适当的通道反转,低导通状态损耗和快速开关,另一方面,低导通状态VGS减少了栅氧化物上的电应力,提高了长期可靠性。了解所选栅极电压对功率器件运行的影响将是实现电气性能和栅极氧化物可靠性之间最佳平衡的基础。本文表明,降低栅极驱动器最大电源电压VGG只影响导通损耗,而关断损耗与VGG无关。实验表征与电热模拟相辅相成,以评估栅极电压对变换器工作的影响。本文表明,在模拟变换器工作时,降低10%的VGG会使器件损耗增加7.6%,结温增加1.4°C。此外,如果通过减小栅极电阻来提高开关速度,则可以补偿导通损耗的影响。这些结果是平衡SiC mosfet系统效率和可靠性的基础。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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