A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET

Abstract

This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.