Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830501
X. Lyu, P. Shrestha, M. Si, Panni Wang, Junkang Li, K. Cheung, Shimeng Yu, P. Ye
In this work, we present the first experimental determination of nucleation time and domain wall (DW) velocity by studying switching dynamics of ferroelectric (FE) hafnium zirconium oxide (HZO). Experimental data and simulation results were used to quantitatively study the switching dynamics. The switch speed is degraded in high aspect ratio devices due to the longer DW propagation time or with dielectric interfacial layer due to the required additional tunneling and trapping time by the leakage current assist switch mechanism.
{"title":"Determination of Domain Wall Velocity and Nucleation Time by Switching Dynamics Studies of Ferroelectric Hafnium Zirconium Oxide","authors":"X. Lyu, P. Shrestha, M. Si, Panni Wang, Junkang Li, K. Cheung, Shimeng Yu, P. Ye","doi":"10.1109/vlsitechnologyandcir46769.2022.9830501","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830501","url":null,"abstract":"In this work, we present the first experimental determination of nucleation time and domain wall (DW) velocity by studying switching dynamics of ferroelectric (FE) hafnium zirconium oxide (HZO). Experimental data and simulation results were used to quantitatively study the switching dynamics. The switch speed is degraded in high aspect ratio devices due to the longer DW propagation time or with dielectric interfacial layer due to the required additional tunneling and trapping time by the leakage current assist switch mechanism.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117346325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830483
W. Chakraborty, P. Shrestha, A. Gupta, R. Saligram, S. Spetalnick, J. Campbell, A. Raychowdhury, S. Datta
Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,1~75μA) with read margin (ΔIRead=IRead,1-IRead,0) ~14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (~8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.
{"title":"Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing","authors":"W. Chakraborty, P. Shrestha, A. Gupta, R. Saligram, S. Spetalnick, J. Campbell, A. Raychowdhury, S. Datta","doi":"10.1109/vlsitechnologyandcir46769.2022.9830483","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830483","url":null,"abstract":"Cryogenic computing requires high-density on-die cache memory with low latency, high bandwidth and energy-efficient access to increase cache hit and maximize processor performance. Here, we experimentally demonstrate, high-speed multi-bit memory operation in 1T SiGe Floating-body RAM (FBRAM) using 22nm FDSOI transistor at 77K, for cryogenic cache memory application. The 1T SiGe FBRAM cell (W/LG=170nm/20nm) at 77K exhibits : (a) record write time of <5ns with write voltage (VWrite) 1.5V; (b) high sense current (IRead,1~75μA) with read margin (ΔIRead=IRead,1-IRead,0) ~14 μA; (c) 2-bit/cell operation; (d) pseudo-static retention (~8x103 s) for single-bit and worst case retention of 100 s for 2-bit per cell, and (e) high write endurance >1012. Array-level benchmarking shows that compared to 6T SRAM, 1T SiGe FBRAM shows 8.3x higher memory density with 2.3x/1.8x gain in read/write energy, 3.3x/1.7x in read/write latency and 4.6x in energy-delay product (EDP) for a cache size of 16MB at 77K. Considering the cooling energy cost, FBRAM exhibit 60% EDP reduction compared to 300K 6T SRAM. Hence, SiGe FBRAM is a promising option for L2/L3 cache in high-performance cryo-computing.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127271329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/VLSITechnologyandCir46769.2022.9830335
Yang Zhao, Yongan Zhang, Yonggan Fu, Xuefeng Ouyang, Cheng Wan, Shang Wu, Anton Banta, M. John, A. Post, M. Razavi, Joseph R. Cavallaro, B. Aazhang, Yingyan Lin
This work presents the first silicon-validated dedicated EGM-to-ECG (G2C) processor, dubbed e-G2C, featuring continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation. e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7× speedup, 3) hybrid dataflows for enhancing near 100% utilization for normal/depth-wise(DW)/point-wise(PW) convolutions (Convs), and 4) an on-chip detection threshold adaptation engine for continuous effectiveness. The achieved 0.14-8.31 µJ/inference energy efficiency outperforms prior arts under similar complexity, promising real-time detection/conversion and possibly life-critical interventions.
{"title":"e-G2C: A 0.14-to-8.31 µJ/Inference NN-based Processor with Continuous On-chip Adaptation for Anomaly Detection and ECG Conversion from EGM","authors":"Yang Zhao, Yongan Zhang, Yonggan Fu, Xuefeng Ouyang, Cheng Wan, Shang Wu, Anton Banta, M. John, A. Post, M. Razavi, Joseph R. Cavallaro, B. Aazhang, Yingyan Lin","doi":"10.1109/VLSITechnologyandCir46769.2022.9830335","DOIUrl":"https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830335","url":null,"abstract":"This work presents the first silicon-validated dedicated EGM-to-ECG (G2C) processor, dubbed e-G2C, featuring continuous lightweight anomaly detection, event-driven coarse/precise conversion, and on-chip adaptation. e-G2C utilizes neural network (NN) based G2C conversion and integrates 1) an architecture supporting anomaly detection and coarse/precise conversion via time multiplexing to balance the effectiveness and power, 2) an algorithm-hardware co-designed vector-wise sparsity resulting in a 1.6-1.7× speedup, 3) hybrid dataflows for enhancing near 100% utilization for normal/depth-wise(DW)/point-wise(PW) convolutions (Convs), and 4) an on-chip detection threshold adaptation engine for continuous effectiveness. The achieved 0.14-8.31 µJ/inference energy efficiency outperforms prior arts under similar complexity, promising real-time detection/conversion and possibly life-critical interventions.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830250
U. Chand, M. Aly, Manohar Lal, Chen Chun-Kuei, S. Hooda, Shih-Hao Tsai, Zihang Fang, H. Veluri, A. Thean
For the first time, we investigated ultra-short-channel ZnO thin-film FETs with Lch = 8 nm with extremely scaled channel thickness tZnO of 3nm, the device exhibits ultra-low sub-pA/µm off leakage (1.2 pA/µm), high electron mobility (µeff = 84 cm2/V•s) with record peak transconductance (Gm,) of 254 μS/μm at VDS = 1 V wrt. reported oxide-based transistors, to date, leading to high on-state current (ION) of 561 μA/μm. We demonstrated the integration of a ZnO access transistor with Al2O3 RRAM to enable a 1T-1R memory cell, suitable for BEOL-embedded memory. We evaluate the system-level benefits of a hardware accelerator for deep learning to employ FET-RRAM as working memory—up to 10X energy-efficiency benefits can be achieved over current baseline configurations.
{"title":"Sub-10nm Ultra-thin ZnO Channel FET with Record-High 561 µA/µm ION at VDS 1V, High µ-84 cm2/V-s and1T-1RRAM Memory Cell Demonstration Memory Implications for Energy-Efficient Deep-Learning Computing","authors":"U. Chand, M. Aly, Manohar Lal, Chen Chun-Kuei, S. Hooda, Shih-Hao Tsai, Zihang Fang, H. Veluri, A. Thean","doi":"10.1109/vlsitechnologyandcir46769.2022.9830250","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830250","url":null,"abstract":"For the first time, we investigated ultra-short-channel ZnO thin-film FETs with Lch = 8 nm with extremely scaled channel thickness tZnO of 3nm, the device exhibits ultra-low sub-pA/µm off leakage (1.2 pA/µm), high electron mobility (µeff = 84 cm2/V•s) with record peak transconductance (Gm,) of 254 μS/μm at VDS = 1 V wrt. reported oxide-based transistors, to date, leading to high on-state current (ION) of 561 μA/μm. We demonstrated the integration of a ZnO access transistor with Al2O3 RRAM to enable a 1T-1R memory cell, suitable for BEOL-embedded memory. We evaluate the system-level benefits of a hardware accelerator for deep learning to employ FET-RRAM as working memory—up to 10X energy-efficiency benefits can be achieved over current baseline configurations.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122511025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830353
Keonhee Cho, Gi-Kryang Kim, J. Oh, Kiryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, T. Song, Seong-ook Jung
This paper presents charge-recycling and charge self-saving techniques in SRAM that lower VMIN while consuming minimal read and write energies. The proposed techniques (with flying CVSS) achieve 250mV (270mV) VMIN improvements in 64-Kb SRAM using 0.080μm2 LV SRAM cell on 14-nm FinFET technology.
{"title":"A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications","authors":"Keonhee Cho, Gi-Kryang Kim, J. Oh, Kiryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, T. Song, Seong-ook Jung","doi":"10.1109/vlsitechnologyandcir46769.2022.9830353","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830353","url":null,"abstract":"This paper presents charge-recycling and charge self-saving techniques in SRAM that lower V<inf>MIN</inf> while consuming minimal read and write energies. The proposed techniques (with flying CV<inf>SS</inf>) achieve 250mV (270mV) V<inf>MIN</inf> improvements in 64-Kb SRAM using 0.080μm<sup>2</sup> LV SRAM cell on 14-nm FinFET technology.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830360
M. V. D. Brink, A. Yen, P. Wijnen, M. Lercel, B. Sluijk
Semiconductors have enabled ever-increasing efficiency in compute and storage of information, as a result of decades of cost-effective scaling of device density and generations of new device technologies. We believe that continued advances in holistic patterning will enable cost-effective scaling of semiconductor devices to continue throughout the 2020s and beyond. We present here key developments across ASML’s holistic product portfolio: the extreme ultraviolet (EUV) lithography roadmap with its 0.33 numerical-aperture (NA) platform and the next-generation 0.55 NA (High-NA) platform, the deep ultraviolet (DUV) roadmap including cutting-edge immersion lithography and cost-efficient mature systems, and key innovations across our optical metrology, electron-beam metrology and inspection portfolio, and our computational lithographic technology. In high-volume manufacturing, the ultimate lithographic performance is only realized by the holistic combination of exposure systems, metrology and inspection tools, and computational-lithographic algorithms. This includes process window optimization during setup, accurate measurement of process capability, and active control to stay within the patterning process window.
{"title":"Holistic Patterning to Advance Semiconductor Manufacturing in the 2020s and Beyond","authors":"M. V. D. Brink, A. Yen, P. Wijnen, M. Lercel, B. Sluijk","doi":"10.1109/vlsitechnologyandcir46769.2022.9830360","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830360","url":null,"abstract":"Semiconductors have enabled ever-increasing efficiency in compute and storage of information, as a result of decades of cost-effective scaling of device density and generations of new device technologies. We believe that continued advances in holistic patterning will enable cost-effective scaling of semiconductor devices to continue throughout the 2020s and beyond. We present here key developments across ASML’s holistic product portfolio: the extreme ultraviolet (EUV) lithography roadmap with its 0.33 numerical-aperture (NA) platform and the next-generation 0.55 NA (High-NA) platform, the deep ultraviolet (DUV) roadmap including cutting-edge immersion lithography and cost-efficient mature systems, and key innovations across our optical metrology, electron-beam metrology and inspection portfolio, and our computational lithographic technology. In high-volume manufacturing, the ultimate lithographic performance is only realized by the holistic combination of exposure systems, metrology and inspection tools, and computational-lithographic algorithms. This includes process window optimization during setup, accurate measurement of process capability, and active control to stay within the patterning process window.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124626937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830238
Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, J. Zhu
In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization.
{"title":"Non-linear CNN-based Read Channel for Hard Disk Drive with 30% Error Rate Reduction and Sequential 200Mbits/second Throughput in 28nm CMOS","authors":"Yuwei Qin, Ruben Purdy, Alec Probst, Ching-Yi Lin, J. Zhu","doi":"10.1109/vlsitechnologyandcir46769.2022.9830238","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830238","url":null,"abstract":"In this work, we present the first ASIC implementation of CNN-based data detection channel for HDDs with 30.3% error rate reduction than the SOTA detection channel. Our chip demonstrates the first methodology of systematically embedding non-linear capacity into HDD read channel with the following features (1) a fully unrolled CNN with dedicated silicon for each convolution layer to produce fast sequential time series data detection at 200 Mbits/s, (2) in total 6 depthwise-separable convolution layers implemented with 2 types of systolic arrays and 100% PE utilization for continuous data flow and high pipelining, (3) integer-only convolutions for improved efficiency at 0.86nJ/bit and 3.99TOPS/W, and (4) pipelined (QReLU) to maintain low-precision feature maps and recover accuracy loss from model quantization.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124731328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents asymmetric simultaneous bidirectional (SBD) transceivers for the next-generation automotive camera link. To realize the SBD operation with the PAM-4 signaling, the proposed wide linear range (WLR) hybrid excludes the voltage-dependent non-linear transconductance (gm) of active elements. A two-step hybrid strategy suppressing the PAM-4 forward channel (FC), including the FFE, is utilized for low power and design simplicity. A Σα hybrid removes only four primary DC levels, and 2nd order gm-capacitor (gmC) low-pass filter (LPF) filters out residual/echoes from the hybrid/channel. An echo canceller (EC) technique is also employed to further reduce the reflections of the PAM-2 back channel (BC). The highly asymmetric SBD transceivers with 12-Gb/s PAM-4 FC and 125-Mb/s PAM-2 BC achieve BER<10-12 over 5-m cable (15.9 dB loss). Prototype chips fabricated in 40-nm technology consume 78.4 mW, exhibiting an FoM of 0.41 pJ/b/dB.
{"title":"0.41-pJ/b/dB Asymmetric Simultaneous Bidirectional Transceivers With PAM-4 Forward and PAM-2 Back Channels for 5-m Automotive Camera Link","authors":"Yunhee Lee, Woonghee Lee, Minkyo Shim, Soyeong Shin, Woo-Seok Choi, D. Jeong","doi":"10.1109/vlsitechnologyandcir46769.2022.9830299","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830299","url":null,"abstract":"This paper presents asymmetric simultaneous bidirectional (SBD) transceivers for the next-generation automotive camera link. To realize the SBD operation with the PAM-4 signaling, the proposed wide linear range (WLR) hybrid excludes the voltage-dependent non-linear transconductance (gm) of active elements. A two-step hybrid strategy suppressing the PAM-4 forward channel (FC), including the FFE, is utilized for low power and design simplicity. A Σα hybrid removes only four primary DC levels, and 2nd order gm-capacitor (gmC) low-pass filter (LPF) filters out residual/echoes from the hybrid/channel. An echo canceller (EC) technique is also employed to further reduce the reflections of the PAM-2 back channel (BC). The highly asymmetric SBD transceivers with 12-Gb/s PAM-4 FC and 125-Mb/s PAM-2 BC achieve BER<10-12 over 5-m cable (15.9 dB loss). Prototype chips fabricated in 40-nm technology consume 78.4 mW, exhibiting an FoM of 0.41 pJ/b/dB.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130567912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830208
Kyoung-Jun Moon, Dong-Ryeol Oh, Younghyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sungno Lee, H. Hwang, H. Shin, Young-Jae Cho, Michael Choi, Jongshin Shin
A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoMWalden of 305fJ/c-s.
提出了一种12b 10GS/s 16通道时间交错(TI) ADC，具有级联输入缓冲器，625MS/s电压电流(V-I)流水SAR ADC和数字处理时斜背景校准。一个采用5nm FinFET的10GS/s TI ADC原型在Nyquist输入下实现48dB SNDR，功耗为625mW，输出功率为305fJ/c-s。
{"title":"A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET","authors":"Kyoung-Jun Moon, Dong-Ryeol Oh, Younghyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sungno Lee, H. Hwang, H. Shin, Young-Jae Cho, Michael Choi, Jongshin Shin","doi":"10.1109/vlsitechnologyandcir46769.2022.9830208","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830208","url":null,"abstract":"A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB SNDR at the Nyquist input with 625mW power consumption, leading to a FoMWalden of 305fJ/c-s.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114835187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-12DOI: 10.1109/vlsitechnologyandcir46769.2022.9830141
K. Seidel, D. Lehninger, R. Hoffmann, T. Ali, M. Lederer, Ricardo Revello, K. Mertens, K. Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, A. Heinig, T. Kämpfe, H. Mähne, K. Bernert, S. Thiem
In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.
{"title":"Memory Array Demonstration of fully integrated 1T-1C FeFET concept with separated ferroelectric MFM device in interconnect layer","authors":"K. Seidel, D. Lehninger, R. Hoffmann, T. Ali, M. Lederer, Ricardo Revello, K. Mertens, K. Biedermann, Yukai Shen, Defu Wang, Matthias Landwehr, A. Heinig, T. Kämpfe, H. Mähne, K. Bernert, S. Thiem","doi":"10.1109/vlsitechnologyandcir46769.2022.9830141","DOIUrl":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830141","url":null,"abstract":"In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124111651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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