Latch-up in Integrated Circuits Under Single and Periodic Electrical Overstress

A. Shemonaev, A. Anikin, K. Epifantsev, P. Skorobogatov
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Abstract

This paper describes the results of sensitivity test to latch-up of several types of ICs (SRAM, EEPROM memory, ADC, microcontroller) caused by single and multiple electrical overstresses. It was shown, that electrical strike with a high-repetition rate increases the sensitivity and vulnerability of ICs to latch-up. The article describes some aspects of the test procedure, which may affect on IC’s sensitivity results.
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单次和周期性电过压下集成电路的锁存现象
本文介绍了几种类型的集成电路(SRAM、EEPROM存储器、ADC、微控制器)的单次和多次电过压引起的锁存灵敏度测试结果。结果表明,高重复频率的电打击增加了集成电路的灵敏度和锁存的脆弱性。本文介绍了测试过程中可能影响集成电路灵敏度结果的几个方面。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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MWENT 2022 Cover Page Latch-up in Integrated Circuits Under Single and Periodic Electrical Overstress The Principle of Increasing Reliability in The Operation of Electronic Craft-Equipment of Cyber-Physical Systems Non-Contact Temperature Setting System for VLSI with High Heat Dissipation Screening of LEDs by the Results of Accelerated Tests Under the Action of Pulsed Current
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