Modeling of through-Silicon-via (TSV) RF characterization using a simplified RLC electrical model

Abstract

This study proposes a simplified RF electrical model for advance chip design circuits using through Silicon via (TSV) interconnection which is passed through complicated material layers in three dimensional (3D) stacks. The structure of TSVs are usually combined with bumps and redistribution layers (RDLs) to achieve its function. The model to describe the TSVs electrical characteristic can be seemed as RLC schematic circuit response to input signal, so an electrical model based on analytical RLC is proposed, and an analytic circuit analysis simulator (ADS) is employed to verify the accuracy of scattering parameter (S parameter) with a 3D electromagnetic field solver (HFSS).