Marios Gourdouparis, Vassilis Alimisis, Christos Dimas, P. Sotiriadis
{"title":"Ultra-Low Power (4nW), 0.6V Fully-Tunable Bump Circuit operating in Sub-threshold regime","authors":"Marios Gourdouparis, Vassilis Alimisis, Christos Dimas, P. Sotiriadis","doi":"10.1109/DTS52014.2021.9498044","DOIUrl":null,"url":null,"abstract":"A compact, ultra-low power (4nW), low supply voltage (0.6V) Gaussian-bump circuit architecture for Radial Basis Functions implementation is presented. It consists of only ten transistors, all operating in sub-threshold. The Gaussians center, height and width are independently and electronically controlled. The proposed architecture is used as a building block to construct a 2 – D Gaussian cascaded bump structure, demonstrating its dimensional scalability. Proper operation, sensitivity and accuracy are confirmed via theoretical analysis and simulation. The presented architectures were realized in TSMC 90nm CMOS process and were simulated using the Cadence IC Suite.","PeriodicalId":158426,"journal":{"name":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTS52014.2021.9498044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A compact, ultra-low power (4nW), low supply voltage (0.6V) Gaussian-bump circuit architecture for Radial Basis Functions implementation is presented. It consists of only ten transistors, all operating in sub-threshold. The Gaussians center, height and width are independently and electronically controlled. The proposed architecture is used as a building block to construct a 2 – D Gaussian cascaded bump structure, demonstrating its dimensional scalability. Proper operation, sensitivity and accuracy are confirmed via theoretical analysis and simulation. The presented architectures were realized in TSMC 90nm CMOS process and were simulated using the Cadence IC Suite.
提出了一种紧凑、超低功耗(4nW)、低电源电压(0.6V)的径向基函数实现高斯碰撞电路结构。它由十个晶体管组成,全部工作在亚阈值下。高斯中心,高度和宽度是独立的和电子控制的。将该结构作为构建块,构造了一个二维高斯级联凹凸结构,证明了其维度可扩展性。通过理论分析和仿真验证了该方法的正确性、灵敏度和精度。该架构在台积电90nm CMOS工艺中实现,并使用Cadence IC Suite进行了仿真。