Hierarchical circuit optimization for analog LSIs using device model refining

Abstract

This paper presents a new approach to circuit optimization, aiming at both short optimization time and high accuracy. Initially, the design variables of the analog circuit module are optimized with simple transistor models with the aim at making design variables closer to the optimal solution speedy. After the design variable vector reaches the near optimal solution, the device model refinement is performed for each device to achieve higher precision. This procedure is repeated until the device model becomes precise enough in the IC environment. The sequence of the device model refinement should be set in advance by designers. A design example indicates that the optimization using device model refining can be carried out in a shorter time than the simulation based approach, whilst achieving a high precision for the solution.