Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514560
T. Cooklev, A. Nishihara, M. Sablatash
The theory of digital filter banks for subband coding is well developed. The purpose of this paper is to develop an analogous framework for the multiresolution analysis of sequences of elements belonging to a finite field. The discussion starts with analysis of decimation and interpolation over finite fields. N-band digital filters are defined over finite fields. Then filter banks are studied. A design theory of orthogonal and biorthogonal filter banks is advanced and examples are given.
{"title":"Theory of filter banks over finite fields","authors":"T. Cooklev, A. Nishihara, M. Sablatash","doi":"10.1109/APCCAS.1994.514560","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514560","url":null,"abstract":"The theory of digital filter banks for subband coding is well developed. The purpose of this paper is to develop an analogous framework for the multiresolution analysis of sequences of elements belonging to a finite field. The discussion starts with analysis of decimation and interpolation over finite fields. N-band digital filters are defined over finite fields. Then filter banks are studied. A design theory of orthogonal and biorthogonal filter banks is advanced and examples are given.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125122688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514537
H. Kunieda, K. Hagiwara
In this paper, we propose a new processor array architecture with effective data storage schemes and its design methodology. The array, called the Memory Sharing Processor Array (MSPA), consists of a processor array with several memory units and their address generation hardware units in order to minimize the data storage. MSPA architecture and its design methodology is similar to the conventional systolic array, but tries to overcome the overlapping data storages, idle processing time and the I/O bottleneck, which mostly degrade the performance of the systolic array. It has practical advantages over the systolic array with regard to area-efficiency, high throughput and practical input schemes. If the number of the concurrent data input ports is limited in a practical situation, the systolic array does not work efficiently. MSPA uses the data access scheme of the common bus architecture, but limits its usage only when it does not cause any data access bottleneck.
{"title":"Effective processor array architecture with shared memory","authors":"H. Kunieda, K. Hagiwara","doi":"10.1109/APCCAS.1994.514537","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514537","url":null,"abstract":"In this paper, we propose a new processor array architecture with effective data storage schemes and its design methodology. The array, called the Memory Sharing Processor Array (MSPA), consists of a processor array with several memory units and their address generation hardware units in order to minimize the data storage. MSPA architecture and its design methodology is similar to the conventional systolic array, but tries to overcome the overlapping data storages, idle processing time and the I/O bottleneck, which mostly degrade the performance of the systolic array. It has practical advantages over the systolic array with regard to area-efficiency, high throughput and practical input schemes. If the number of the concurrent data input ports is limited in a practical situation, the systolic array does not work efficiently. MSPA uses the data access scheme of the common bus architecture, but limits its usage only when it does not cause any data access bottleneck.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514631
Tian-Hu Yu
Edges characterize object boundaries, and an edge point can be thought of as the pixel location of abrupt gray-level changes. Most edge detection algorithms are based on generation of gradient images and thresholding of gradient images. There are two problems in detecting edges of a video sequence in a telesign system. One is that the linear gradient does not match Weber's law, and the other is difficulty in finding an appropriate threshold efficiently. In this paper, we introduce a concept of nonlinear gradient to match Weber's law, i.e., to detect perceptual edges. It is easy to determine a proper threshold for the nonlinear gradient images. Based on the advantages of the nonlinear gradient, the author found an important application in the telesign system.
{"title":"Nonlinear gradient-based edge detection algorithms in the telesign system","authors":"Tian-Hu Yu","doi":"10.1109/APCCAS.1994.514631","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514631","url":null,"abstract":"Edges characterize object boundaries, and an edge point can be thought of as the pixel location of abrupt gray-level changes. Most edge detection algorithms are based on generation of gradient images and thresholding of gradient images. There are two problems in detecting edges of a video sequence in a telesign system. One is that the linear gradient does not match Weber's law, and the other is difficulty in finding an appropriate threshold efficiently. In this paper, we introduce a concept of nonlinear gradient to match Weber's law, i.e., to detect perceptual edges. It is easy to determine a proper threshold for the nonlinear gradient images. Based on the advantages of the nonlinear gradient, the author found an important application in the telesign system.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114899529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514607
K. Ueda
This paper reviews the chip fabrication services for universities in North America and European countries. One feature of these services is the adoption of a chip fabrication system (called Multiproject Chip) that makes it possible for users at universities to fabricate chips at an extremely low cost. The key idea of the multiproject chip system is that sharing a chip or a wafer among several projects makes it possible to greatly reduce manufacturing costs. The paper covers MOSIS (USA), CMC (Canada), CMP (France), EIS (Germany) and Eurochip (Europe) services. Those services have clearly been making great contributions to increasing the expertise in LSI design at universities.
{"title":"Chip fabrication services for universities in North America and Europe","authors":"K. Ueda","doi":"10.1109/APCCAS.1994.514607","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514607","url":null,"abstract":"This paper reviews the chip fabrication services for universities in North America and European countries. One feature of these services is the adoption of a chip fabrication system (called Multiproject Chip) that makes it possible for users at universities to fabricate chips at an extremely low cost. The key idea of the multiproject chip system is that sharing a chip or a wafer among several projects makes it possible to greatly reduce manufacturing costs. The paper covers MOSIS (USA), CMC (Canada), CMP (France), EIS (Germany) and Eurochip (Europe) services. Those services have clearly been making great contributions to increasing the expertise in LSI design at universities.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115536269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514551
J. Chang, C. Shung
Reed-Solomon (RS) code is one of the most important error controlling codes in digital communications. It is especially powerful for multiple error correction, thus suitable for random and burst error correction. In this paper, we propose a lookforward architecture that can reduce the number of cycles in the longer pipeline stage, thus resulting in a more efficient use of the pipelined structure. We implemented a (255,239) RS codec chip using the lookforward architecture. Both the code length and error correcting capability of the codec chip are programmable. This chip consists of 310,000 transistors in 61 mm/sup 2/ area with a 0.8 /spl mu/m SPDM CMOS technology.
{"title":"A high speed Reed-Solomon codec chip using lookforward architecture","authors":"J. Chang, C. Shung","doi":"10.1109/APCCAS.1994.514551","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514551","url":null,"abstract":"Reed-Solomon (RS) code is one of the most important error controlling codes in digital communications. It is especially powerful for multiple error correction, thus suitable for random and burst error correction. In this paper, we propose a lookforward architecture that can reduce the number of cycles in the longer pipeline stage, thus resulting in a more efficient use of the pipelined structure. We implemented a (255,239) RS codec chip using the lookforward architecture. Both the code length and error correcting capability of the codec chip are programmable. This chip consists of 310,000 transistors in 61 mm/sup 2/ area with a 0.8 /spl mu/m SPDM CMOS technology.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122892821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514571
Gen-Kwo Lee, S. Gelfand, M. Fitz
In this paper we propose a family of Bayesian conditional decision feedback estimators (BCDFE) suitable for blind equalization. The BCDFEs are indexed by two parameters: a "chip" length and an estimation lag. These algorithms can be used with estimation lags greater than the equivalent channel length, and have a complexity which is exponential in the chip length but only linear in the estimation lag. Recursive channel estimation is combined with the BCDFE to produce high performance in unknown channel equalization. Extensive simulations characterize the performance of the BCDFE for uncoded linear modulations over unknown channels. Also, a simple adaptive complexity reduction scheme can be combined with the BCDFE resulting in further substantial reductions in complexity, especially for large constellations.
{"title":"Bayesian decision feedback techniques for blind equalization","authors":"Gen-Kwo Lee, S. Gelfand, M. Fitz","doi":"10.1109/APCCAS.1994.514571","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514571","url":null,"abstract":"In this paper we propose a family of Bayesian conditional decision feedback estimators (BCDFE) suitable for blind equalization. The BCDFEs are indexed by two parameters: a \"chip\" length and an estimation lag. These algorithms can be used with estimation lags greater than the equivalent channel length, and have a complexity which is exponential in the chip length but only linear in the estimation lag. Recursive channel estimation is combined with the BCDFE to produce high performance in unknown channel equalization. Extensive simulations characterize the performance of the BCDFE for uncoded linear modulations over unknown channels. Also, a simple adaptive complexity reduction scheme can be combined with the BCDFE resulting in further substantial reductions in complexity, especially for large constellations.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129457828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514540
S. Iimuro, N. Sugino, A. Nishihara, N. Fujii
Methods to derive an efficient memory access pattern for DSPs of which memory is accessed only by address registers (ARs) are discussed. Variables in a program and AR operations are modeled by an access graph. A novel memory allocation method, which removes cycles and forks in a given access graph, and decides an efficient address location of variables in memory space, is proposed. In order to utilize multiple ARs, methods to assign variables into ARs are investigated. The method based on min-cut algorithm is superior to the method based on the simulated annealing technique. The proposed methods are applied to the compiler for DSP56000 and generated codes for several examples are very much improved.
{"title":"Code optimization method utilizing memory addressing operation and its application to DSP compiler","authors":"S. Iimuro, N. Sugino, A. Nishihara, N. Fujii","doi":"10.1109/APCCAS.1994.514540","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514540","url":null,"abstract":"Methods to derive an efficient memory access pattern for DSPs of which memory is accessed only by address registers (ARs) are discussed. Variables in a program and AR operations are modeled by an access graph. A novel memory allocation method, which removes cycles and forks in a given access graph, and decides an efficient address location of variables in memory space, is proposed. In order to utilize multiple ARs, methods to assign variables into ARs are investigated. The method based on min-cut algorithm is superior to the method based on the simulated annealing technique. The proposed methods are applied to the compiler for DSP56000 and generated codes for several examples are very much improved.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130422165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514544
A. Yamada, T. Yamazaki, N. Ishiura, I. Shirakawa, T. Kambe
A new approach is described for the datapath scheduling of behavioral descriptions containing nested conditional branches of arbitrary structures. This paper formulates a time-constrained scheduling problem as a 0-1 integer programming problem, in which each constraint is expressed in the form of a Boolean function, and a satisfiability problem is defined by the product of the Boolean functions. A procedure is then described, which intends to seek an optimal solution by means of a branch-and-bound method on a binary decision diagram representing the satisfiability problem. Experimental results show that our approach attains better solutions than other existing methods.
{"title":"Datapath scheduling for conditional resource sharing","authors":"A. Yamada, T. Yamazaki, N. Ishiura, I. Shirakawa, T. Kambe","doi":"10.1109/APCCAS.1994.514544","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514544","url":null,"abstract":"A new approach is described for the datapath scheduling of behavioral descriptions containing nested conditional branches of arbitrary structures. This paper formulates a time-constrained scheduling problem as a 0-1 integer programming problem, in which each constraint is expressed in the form of a Boolean function, and a satisfiability problem is defined by the product of the Boolean functions. A procedure is then described, which intends to seek an optimal solution by means of a branch-and-bound method on a binary decision diagram representing the satisfiability problem. Experimental results show that our approach attains better solutions than other existing methods.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126679371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514602
R. Kang, Tasi-Chung Yu, Chung-Yu Wu
In this paper, a new structure is proposed to implement a programmable gain controller with a wide dynamic range. The timing-duty controlled structure determines the attenuation values by changing the ratio of the integration time between the desired attenuation value and unity gain instead of the resistor or capacitor ratios. It reduces the chip area by applying the timing-duty controlled concept on switched capacitor (SC) circuits. But in the original timing-duty controlled circuit the system clock frequency would be too high to be implemented in order to have a high resolution. A new timing-duty controlled programmable gain controller (TDGC) is proposed and reduces the required system clock frequency by one-third and one-fourth successfully. There are two advantages of this new structure: one is the absence of the selectable capacitor array - thus it takes up less chip area than ordinary SC circuits. The other is that the TDGC circuit is used more efficiently by modifying the timing diagram and is feasible to be applied to the SC circuits. The proposed programmable gain controller (PGC) circuit has 80 level settings of the LOSS range from 0 dB to -79 dB by a step of -1 dB. It has monotonically logarithmic increments with maximum deviation of -0.53 dB in the range of 0 dB to -59 dB and -0.83 dB in the range of 0 dB to -79 dB.
{"title":"A new CMOS programmable gain controller with a wide dynamic range","authors":"R. Kang, Tasi-Chung Yu, Chung-Yu Wu","doi":"10.1109/APCCAS.1994.514602","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514602","url":null,"abstract":"In this paper, a new structure is proposed to implement a programmable gain controller with a wide dynamic range. The timing-duty controlled structure determines the attenuation values by changing the ratio of the integration time between the desired attenuation value and unity gain instead of the resistor or capacitor ratios. It reduces the chip area by applying the timing-duty controlled concept on switched capacitor (SC) circuits. But in the original timing-duty controlled circuit the system clock frequency would be too high to be implemented in order to have a high resolution. A new timing-duty controlled programmable gain controller (TDGC) is proposed and reduces the required system clock frequency by one-third and one-fourth successfully. There are two advantages of this new structure: one is the absence of the selectable capacitor array - thus it takes up less chip area than ordinary SC circuits. The other is that the TDGC circuit is used more efficiently by modifying the timing diagram and is feasible to be applied to the SC circuits. The proposed programmable gain controller (PGC) circuit has 80 level settings of the LOSS range from 0 dB to -79 dB by a step of -1 dB. It has monotonically logarithmic increments with maximum deviation of -0.53 dB in the range of 0 dB to -59 dB and -0.83 dB in the range of 0 dB to -79 dB.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123909623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514531
Sau-Gee Chen, Jiann-Cherng Lee, Chieh-Chih Li
Several new real-time systolic implementations for three popular Kalman filtering algorithms are presented. These architectures are all composed of two units of systolic arrays, where the first one is based on three new, systolic arrays for matrix multiplications and additions, while the second one is a conventional systolic array for matrix inversion. Mathematical formulations of the three Kalman filtering algorithms are scheduled for the best deployment of those systolic arrays. This results in nine new systolic Kalman filters. Among them, one has the best performances in both speed and hardware complexities among the existing architectures. Specifically, this architecture has a smaller number of O(2n/sup 2/) PEs than O(2.5n/sup 2/) PEs of the best known structures, and a highest throughput rate.
{"title":"Systolic implementation of Kalman filter","authors":"Sau-Gee Chen, Jiann-Cherng Lee, Chieh-Chih Li","doi":"10.1109/APCCAS.1994.514531","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514531","url":null,"abstract":"Several new real-time systolic implementations for three popular Kalman filtering algorithms are presented. These architectures are all composed of two units of systolic arrays, where the first one is based on three new, systolic arrays for matrix multiplications and additions, while the second one is a conventional systolic array for matrix inversion. Mathematical formulations of the three Kalman filtering algorithms are scheduled for the best deployment of those systolic arrays. This results in nine new systolic Kalman filters. Among them, one has the best performances in both speed and hardware complexities among the existing architectures. Specifically, this architecture has a smaller number of O(2n/sup 2/) PEs than O(2.5n/sup 2/) PEs of the best known structures, and a highest throughput rate.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124185128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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